Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
The Cross Entropy Method: A Unified Approach To Combinatorial Optimization, Monte-carlo Simulation (Information Science and Statistics)
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A technique for low energy mapping and routing in network-on-chip architectures
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Mapping and configuration methods for multi-use-case networks on chips
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An architectural co-synthesis algorithm for energy-aware network-on-chip design
Proceedings of the 2007 ACM symposium on Applied computing
Link-load balance aware mapping and routing for NoC
WSEAS Transactions on Circuits and Systems
Achieving predictable performance through better memory controller placement in many-core CMPs
Proceedings of the 36th annual international symposium on Computer architecture
Chip-set for video display of multimedia information
IEEE Transactions on Consumer Electronics
Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
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Due to technology scaling, it is expected that future chips would integrate tens to hundreds of functional units. The growing power and design costs limit the benefit of continuously increasing the universality and complexity of these units and motivate the usage of specialized hardware modules. These modules are likely to be replicated in order to exploit the inherent parallelism of many tasks. This trend already exists in CMPs (moving from multi-core to many-cores), ASSPs and FPGAs. In this paper, we revisit the network on-chip (NoC) mapping problem in light of this expected trend. Specifically, we leverage the use of on-chip replicated specialized modules to minimize traffic and hence to reduce the power consumed by the NoC. We further improve the interconnect efficiency by making the mapping algorithm aware of the set of modules traversed by application data. To this end, we present an enhanced modeling of the resources and timing requirements within a system on-chip (SoC). We evaluate the benefit of the proposed approach and show a significant reduction in the cost of communication.