Heuristic Algorithms for Scheduling Independent Tasks on Nonidentical Processors
Journal of the ACM (JACM)
Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A technique for low energy mapping and routing in network-on-chip architectures
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mapping Applications to Tiled Multiprocessor Embedded Systems
ACSD '07 Proceedings of the Seventh International Conference on Application of Concurrency to System Design
Achieving network on chip fault tolerance by adaptive remapping
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
The era of many-modules SoC: revisiting the NoC mapping problem
Proceedings of the 2nd International Workshop on Network on Chip Architectures
A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints
ACM Transactions on Architecture and Code Optimization (TACO)
SOC'09 Proceedings of the 11th international conference on System-on-chip
Combining mapping and partitioning exploration for NoC-based embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
An ILP formulation for task mapping and scheduling on multi-core architectures
Proceedings of the Conference on Design, Automation and Test in Europe
A task remapping technique for reliable multi-core embedded systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Evolutionary Computation
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mapping on multi/many-core systems: survey of current and emerging trends
Proceedings of the 50th Annual Design Automation Conference
Reliability and performance optimization of pipelined real-time systems
Journal of Parallel and Distributed Computing
Journal of Systems Architecture: the EUROMICRO Journal
Using task migration to improve non-contiguous processor allocation in NoC-based CMPs
Journal of Systems Architecture: the EUROMICRO Journal
A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project
Microprocessors & Microsystems
Maintaining real-time application timing similarity for defect-tolerant NoC-based many-core systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
Energy-aware task mapping and scheduling for reliable embedded computing systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
Communication and migration energy aware task mapping for reliable multiprocessor systems
Future Generation Computer Systems
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As CMOS technology scales down into the deep-submicron domain, the aspects of fault tolerance in complex Networks-on-Chip (NoCs) architectures are assuming an increasing relevance. Task remapping is a software based solution for dealing with permanent failures in processing elements in the NoC. In this work, we formulate the optimal task mapping problem for mesh-based NoC multiprocessors with deterministic routing as an integer linear programming (ILP) problem with the objective of minimizing the communication traffic in the system and the total execution time of the application. We find the optimal mappings at design time for all scenarios where single-faults occur in the processing nodes. We propose heuristics for the online task remapping problem and compare their performance with the optimal solutions.