Min-max linear programming and the timing analysis of digital circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Proceedings of the 6th international workshop on Hardware/software codesign
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Feasibility of semiring-based timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the Conference on Design, Automation and Test in Europe
Branch-and-Bound for Model Selection and Its Computational Complexity
IEEE Transactions on Knowledge and Data Engineering
Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Quantifying similarities between timed systems
FORMATS'05 Proceedings of the Third international conference on Formal Modeling and Analysis of Timed Systems
| Hi-index | 0.00 |
Many-core Network-on-Chip (NoC) processors are emerging in broad application areas, including those with timing requirements, such as real-time and multimedia applications. Typically, these processors employ core-level backup to improve yield. However, when defective cores are replaced by backup ones, the NoC topology changes. Consequently, a fine-tuned application based on timing parameters given by one topology may not meet the expected timing behavior under the new one. We first develop a metric to measure timing similarity of an application on different NoC topologies and then propose mixed binary quadratic programming and greedy algorithms to reconfigure a defect-tolerant many-core NoC.