Power-aware communication optimization for networks-on-chips with voltage scalable links
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated memory-aware application distribution for Multi-processor System-on-Chips
Journal of Systems Architecture: the EUROMICRO Journal
A multiobjective evolutionary algorithm-based optimisation model for network on chip synthesis
International Journal of Innovative Computing and Applications
Designing efficient irregular networks for heterogeneous systems-on-chip
Journal of Systems Architecture: the EUROMICRO Journal
Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions
Journal of Systems Architecture: the EUROMICRO Journal
ADAM: run-time agent-based distributed application mapping for on-chip communication
Proceedings of the 45th annual Design Automation Conference
Minimizing virtual channel buffer for routers in on-chip communication architectures
Proceedings of the conference on Design, automation and test in Europe
A Link-Load Balanced Low Energy Mapping and Routing for NoC
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
A Communication-Aware Topological Mapping Technique for NoCs
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
A topology design customization approach for STNoC
Proceedings of the 2nd international conference on Nano-Networks
Link-load balance aware mapping and routing for NoC
WSEAS Transactions on Circuits and Systems
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
An accurate and efficient performance analysis approach based on queuing model for Network on Chip
Proceedings of the 2009 International Conference on Computer-Aided Design
Optimal application mapping on NoC infrastructure using NSGA-II and microGA
INES'09 Proceedings of the IEEE 13th international conference on Intelligent Engineering Systems
Evolutionary IP assignment for efficient NoC-based system design using multi-objective optimization
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
SOC'09 Proceedings of the 11th international conference on System-on-chip
Scheduling framework for real-time dependable NoC-based systems
SOC'09 Proceedings of the 11th international conference on System-on-chip
Application mapping of mesh based-NoC using multi-objective genetic algorithm
International Journal of Computers and Applications
Efficient mapping of an image processing application for a network-on-chip based implementation
International Journal of High Performance Systems Architecture
A case for lifetime-aware task mapping in embedded chip multiprocessors
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Journal of Systems Architecture: the EUROMICRO Journal
Process scheduling for future multicore processors
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip
Proceedings of the 38th annual international symposium on Computer architecture
Artificial bee colony based mapping for application specific network-on-chip design
ICSI'11 Proceedings of the Second international conference on Advances in swarm intelligence - Volume Part I
Expert Systems with Applications: An International Journal
Analytical derivation of traffic patterns in cache-coherent shared-memory systems
Microprocessors & Microsystems
A minimal average accessing time scheduler for multicore processors
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part II
Efficient switches for network-on-chip based embedded systems
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Exploration of heuristic scheduling algorithms for 3D multicore processors
Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
A greedy heuristic approximation scheduling algorithm for 3d multicore processors
Euro-Par'11 Proceedings of the 2011 international conference on Parallel Processing
MpAssign: A Framework for Solving the Many-Core Platform Mapping Problem
Software—Practice & Experience
Integrating Memory Optimization with Mapping Algorithms for Multi-Processors System-on-Chip
ACM Transactions on Embedded Computing Systems (TECS)
A multi-objective mapping strategy for application specific emesh network-on-chip (noc)
ICSI'12 Proceedings of the Third international conference on Advances in Swarm Intelligence - Volume Part I
Application-to-core mapping policies to reduce memory interference in multi-core systems
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Optimal placement of frequently accessed IPs in mesh NoCs
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Reliable noc mapping based on scatter search
ICICA'12 Proceedings of the Third international conference on Information Computing and Applications
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Efficient genetic based topological mapping using analytical models for on-chip networks
Journal of Computer and System Sciences
Maintaining real-time application timing similarity for defect-tolerant NoC-based many-core systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
Energy and buffer aware application mapping for networks-on-chip with self similar traffic
Journal of Systems Architecture: the EUROMICRO Journal
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Network on Chip (NoC) is a new paradigm fordesigning core based System on Chip which supports highdegree of reusability and is scalable. In this paper wedescribe an efficient two-step genetic algorithm that hasbeen used to build a tool for mapping an application,described by a parameterized task graph, on to a NoCarchitecture with a two dimensional mesh of switches as acommunication backbone. The computational resources inNoC consists of a set of heterogenous IP cores. Ouralgorithm finds a mapping of the vertices of the taskgraph to available cores so that the overall execution timeof the task graph is minimized. We have developed a NoCarchitecture specific communication delay model toestimate the execution time. Our algorithm is able tohandle large task graphs and provide near optimalmapping in a few minutes on a PC platform. Our tool alsoprovides facilities for specifying NoC architecture,generation and viewing synthetic task graphs and viewingthe progress of the genetic algorithm as it converges to asolution.