Computers and Intractability; A Guide to the Theory of NP-Completeness
Computers and Intractability; A Guide to the Theory of NP-Completeness
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application Mapping onto Mesh Structured Network-on-Chip Using Particle Swarm Optimization
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
Application-Aware Topology Reconfiguration for On-Chip Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Network-on-Chip (NoC) is a promising interconnection solution for systems on chip. Mapping Intellectual Property (IP) cores onto NoC architecture is an important phase of NoC design. It affects heavily the NoC performance. In this paper, we propose a multi-objectives optimization algorithm based on Scatter Search for NoC mapping. We introduce reliability evaluation into NoC mapping in order to achieve high performance and reliable NoC architectures. Experimental results show that our algorithm achieves low power consumption, little communication time, balanced link load and high reliability, compared to other traditional evolutional algorithms.