The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Proceedings of the 6th international workshop on Hardware/software codesign
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Codex-dp: co-design of communicating systems using dynamic programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Distributed Multimedia System Design: A Holistic Perspective
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Packetization and routing analysis of on-chip multiprocessor networks
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low latency router supporting adaptivity for on-chip interconnects
Proceedings of the 42nd annual Design Automation Conference
A low-power crossroad switch architecture and its core placement for network-on-chip
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A technique for low energy mapping and routing in network-on-chip architectures
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Mapping and configuration methods for multi-use-case networks on chips
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Time and energy efficient mapping of embedded applications onto NoCs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
SAGA: synthesis technique for guaranteed throughput NoC architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
NoCEE: energy macro-model extraction methodology for network on chip routers
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A low complexity heuristic for design of custom network-on-chip architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Proceedings of the 33rd annual international symposium on Computer Architecture
System level design paradigms: Platform-based design and communication synthesis
Proceedings of the 41st annual Design Automation Conference
Communication latency aware low power NoC synthesis
Proceedings of the 43rd annual Design Automation Conference
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A design methodology for application-specific networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
Automatic run-time extraction of communication graphs from multithreaded applications
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Layout aware design of mesh based NoC architectures
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
An architectural co-synthesis algorithm for energy-aware network-on-chip design
Proceedings of the 2007 ACM symposium on Applied computing
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Implementing DSP Algorithms with On-Chip Networks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy optimization of multiprocessor systems on chip by voltage selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Arbiter synthesis approach for SoC multi-processor systems
Computers and Electrical Engineering
NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A multiobjective evolutionary algorithm-based optimisation model for network on chip synthesis
International Journal of Innovative Computing and Applications
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Energy efficient streaming applications with guaranteed throughput on MPSoCs
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A topology design customization approach for STNoC
Proceedings of the 2nd international conference on Nano-Networks
Application-specific networks-on-chip topology customization using network partitioning
IFMT '08 Proceedings of the 1st international forum on Next-generation multicore/manycore technologies
A voltage-frequency island aware energy optimization framework for networks-on-chip
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Robust concurrent online testing of network-on-chip-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 19th ACM Great Lakes symposium on VLSI
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Achieving predictable performance through better memory controller placement in many-core CMPs
Proceedings of the 36th annual international symposium on Computer architecture
Increasing NoC power estimation accuracy through a rate-based model
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A high abstraction, high accuracy power estimation model for networks-on-chip
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Automated technique for design of NoC with minimal communication latency
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Custom networks-on-chip architectures with multicast routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Breaking adaptive multicast deadlock by virtual channel address/data FIFO decoupling
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal application mapping on NoC infrastructure using NSGA-II and microGA
INES'09 Proceedings of the IEEE 13th international conference on Intelligent Engineering Systems
Evolutionary IP assignment for efficient NoC-based system design using multi-objective optimization
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
Throughput-oriented NoC topology generation and analysis for high performance SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints
ACM Transactions on Architecture and Code Optimization (TACO)
SOC'09 Proceedings of the 11th international conference on System-on-chip
Application mapping of mesh based-NoC using multi-objective genetic algorithm
International Journal of Computers and Applications
Systematic customization of on-chip crossbar interconnects
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Proceedings of the 2010 ACM Symposium on Applied Computing
Efficient mapping of an image processing application for a network-on-chip based implementation
International Journal of High Performance Systems Architecture
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Hybrid network on chip (HNoC): local buses with a global mesh architecture
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Leveraging partially faulty links usage for enhancing yield and performance in networks-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A Safari Through the MPSoC Run-Time Management Jungle
Journal of Signal Processing Systems
Leveraging application-level requirements in the design of a NoC for a 4G SoC: a case study
Proceedings of the Conference on Design, Automation and Test in Europe
Convex-based DOR routing for virtualization of NoC
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Distance constrained mapping to support NoC platforms based on source routing
Euro-Par'09 Proceedings of the 2009 international conference on Parallel processing
State observer controller design for packets flow control in networks-on-chip
The Journal of Supercomputing
A3MAP: architecture-aware analytic mapping for networks-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Floorplanning and topology generation for application-specific network-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Journal of Systems Architecture: the EUROMICRO Journal
Design of network-on-chip architectures with a genetic algorithm-based technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CAFES: A framework for intrachip application modeling and communication architecture design
Journal of Parallel and Distributed Computing
Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
ScatterD: Spatial deployment optimization with hybrid heuristic/evolutionary algorithms
ACM Transactions on Autonomous and Adaptive Systems (TAAS)
Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework
Proceedings of the 24th symposium on Integrated circuits and systems design
Multi-task dynamic mapping onto NoC-based MPSoCs
Proceedings of the 24th symposium on Integrated circuits and systems design
Energy-efficient cache coherence protocol for NoC-based MPSoCs
Proceedings of the 24th symposium on Integrated circuits and systems design
Artificial bee colony based mapping for application specific network-on-chip design
ICSI'11 Proceedings of the Second international conference on Advances in swarm intelligence - Volume Part I
Expert Systems with Applications: An International Journal
Analytical derivation of traffic patterns in cache-coherent shared-memory systems
Microprocessors & Microsystems
Partitioning and mapping on NoC-Based MPSoC: an energy consumption saving approach
Proceedings of the 4th International Workshop on Network on Chip Architectures
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Realization of video object plane decoder on on-chip network architecture
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Streamlined network-on-chip for multicore embedded architectures
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Model-based analysis tools for component synthesis
FMCO'10 Proceedings of the 9th international conference on Formal Methods for Components and Objects
A3MAP: Architecture-aware analytic mapping for networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
A signature-based power model for MPSoC on FPGA
VLSI Design
MpAssign: A Framework for Solving the Many-Core Platform Mapping Problem
Software—Practice & Experience
A multi-objective mapping strategy for application specific emesh network-on-chip (noc)
ICSI'12 Proceedings of the Third international conference on Advances in Swarm Intelligence - Volume Part I
Application-to-core mapping policies to reduce memory interference in multi-core systems
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Minimizing power supply noise through harmonic mappings in networks-on-chip
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An automatic design flow for mapping application onto a 2D mesh NoC architecture
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Optimal placement of frequently accessed IPs in mesh NoCs
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Reliable noc mapping based on scatter search
ICICA'12 Proceedings of the Third international conference on Information Computing and Applications
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Parameter-optimized simulated annealing for application mapping on networks-on-chip
LION'12 Proceedings of the 6th international conference on Learning and Intelligent Optimization
Developing Domain-Knowledge Evolutionary Algorithms for Network-on-Chip Application Mapping
Microprocessors & Microsystems
Efficient genetic based topological mapping using analytical models for on-chip networks
Journal of Computer and System Sciences
Journal of Computer and System Sciences
Mapping on multi/many-core systems: survey of current and emerging trends
Proceedings of the 50th Annual Design Automation Conference
A multi-agent framework for thermal aware task migration in many-core systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
UNISM: unified scheduling and mapping for general networks on chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CusNoC: fast full-chip custom NoC generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Congestion-aware scheduling for NoC-based reconfigurable systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Deflection routing in 3D network-on-chip with limited vertical bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Application-Specific Network-on-Chip synthesis with flexible router Placement
Journal of Systems Architecture: the EUROMICRO Journal
Are virtual channels the bottleneck of priority-aware wormhole-switched NoC-based many-cores?
Proceedings of the 21st International conference on Real-Time Networks and Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design space exploration for streaming applications on multiprocessors with guaranteed service NoC
Proceedings of the Sixth International Workshop on Network on Chip Architectures
Empirical and theoretical lower bounds on energy consumption for networks on chip
Proceedings of the Sixth International Workshop on Network on Chip Architectures
Design space exploration of thermal-aware many-core systems
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Systems Architecture: the EUROMICRO Journal
Energy and buffer aware application mapping for networks-on-chip with self similar traffic
Journal of Systems Architecture: the EUROMICRO Journal
Providing multiple hard latency and throughput guarantees for packet switching networks on chip
Computers and Electrical Engineering
NoC contention analysis using a branch-and-prune algorithm
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure
Computers and Electrical Engineering
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In this paper, we present an algorithm which automatically maps the IPs/cores onto a generic regular Network on Chip (NoC) architecture such that the total communication energy is minimized. At the same time, the performance of the mapped system is guaranteed to satisfy the specified constraints through bandwidth reservation. As the main contribution, we first formulate the problem of energy-aware mapping, in a topological sense, and then propose an efficient branch-and-bound algorithm to solve it. Experimental results show that the proposed algorithm is very fast and robust, and significant energy savings can be achieved. For instance, for a complex video/audio SoC design, on average, 60.4% energy savings have been observed compared to an ad-hoc implementation.