Proceedings of the 6th international workshop on Hardware/software codesign
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A Multi-Objective Evolutionary Algorithm Based Optimization Model for Network-on-Chip Synthesis
ITNG '07 Proceedings of the International Conference on Information Technology
Muiltiobjective optimization using nondominated sorting in genetic algorithms
Evolutionary Computation
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
Breaking adaptive multicast deadlock by virtual channel address/data FIFO decoupling
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Efficient mapping of an image processing application for a network-on-chip based implementation
International Journal of High Performance Systems Architecture
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Network-on-chip (NoC) are considered the next generation of communication infrastructure, which will be omnipresent in most of industry, office and personal electronic systems. In platform-based methodology, an application is implemented by a set of collaborating intellectual properties (IPs) blocks. In this paper, we use two multi-objective evolutionay algorithms to address the problem of selecting the most adequate set of IPs (from an available library) that best implements the application. The IP selection optimization is driven by the minimization of hardware area, total execution time and power consumption.