Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Planar-adaptive routing: low-cost adaptive networks for multiprocessors
Journal of the ACM (JACM)
Proceedings of the 6th international workshop on Hardware/software codesign
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
A Delay Model for Router Microarchitectures
IEEE Micro
Deadlock-Free Multicast Wormhole Routing in 2-D Mesh Multicomputers
IEEE Transactions on Parallel and Distributed Systems
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Enforcing in-order packet delivery in system area networks with adaptive routing
Journal of Parallel and Distributed Computing - Special issue: Design and performance of networks for super-, cluster-, and grid-computing: Part I
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Proceedings of the 33rd annual international symposium on Computer Architecture
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip
IEEE Transactions on Computers
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evolutionary IP assignment for efficient NoC-based system design using multi-objective optimization
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
Microprocessors & Microsystems
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As computing goes to system-on-chip era, on-chip network becomes an essential infrastructure for on-chip modules (cores) communication. 2D-Mesh is the most common on-chip network topology providing high throughput point-to-point communication due to its simplicity and regularity. A well-designed 2D-Mesh wormhole router should be deadlock free while supporting multicast and adaptive routing. Unfortunately, there exists no router design providing all these characteristics concurrently. In this paper, we propose an on-chip address-data decoupled FIFO wormhole router which supports adaptive routing, native multicast and deadlock free network guarantee. For a network using a 30-flit packet, our wormhole router increases the area efficiency by 49.5% compared with a virtual cut-through router.