Linear-programming-based techniques for synthesis of network-on-chip architectures

Authors:
Krishnan Srinivasan;Karam S. Chatha;Goran Konjevod
Affiliations:
Department of Computer Science and Engineering, Arizona State University, Tempe, AZ;Department of Computer Science and Engineering, Arizona State University, Tempe, AZ;Department of Computer Science and Engineering, Arizona State University, Tempe, AZ
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2006

Citing 24
Cited 47

Deadlock-Free Message Routing in Multiprocessor Interconnection Networks

IEEE Transactions on Computers
Characterization of Deadlocks in k-ary n-Cube Networks

IEEE Transactions on Parallel and Distributed Systems
Floorplan sizing by linear programming approximation

Proceedings of the 37th Annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
VISI Physical Design Automation: Theory and Practice

VISI Physical Design Automation: Theory and Practice
Readings in Hardware/Software Co-Design

Readings in Hardware/Software Co-Design
Computers and Intractability: A Guide to the Theory of NP-Completeness

Computers and Intractability: A Guide to the Theory of NP-Completeness
Networks on Chips: A New SoC Paradigm

Computer
The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs

IEEE Micro
Leakage power modeling and optimization in interconnection networks

Proceedings of the 2003 international symposium on Low power electronics and design
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture

DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Efficient Synthesis of Networks On Chip

ICCD '03 Proceedings of the 21st International Conference on Computer Design
Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints

Proceedings of the conference on Design, automation and test in Europe - Volume 1
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip

Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Power and Performance Model for Network-on-Chip Architectures

Proceedings of the conference on Design, automation and test in Europe - Volume 2
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures

ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Cost considerations in network on chip

Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Quality-of-service and error control techniques for mesh-based network-on-chip architectures

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Multi-Objective Mapping for Mesh-Based NoC Architectures

CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Energy-aware mapping for tile-based NoC architectures under performance constraints

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A global wiring paradigm for deep submicron design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A linear programming-based algorithm for floorplanning in VLSI design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A low complexity heuristic for design of custom network-on-chip architectures

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Layout aware design of mesh based NoC architectures

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
An ilp based approach to reducing energy consumption in nocbased CMPS

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Elastic Flow in an Application Specific Network-on-Chip

Electronic Notes in Theoretical Computer Science (ENTCS)
NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Application-specific network-on-chip architecture synthesis based on set partitions and Steiner trees

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions

Journal of Systems Architecture: the EUROMICRO Journal
Link-load balance aware mapping and routing for NoC

WSEAS Transactions on Circuits and Systems
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design

Journal of Systems Architecture: the EUROMICRO Journal
Energy efficient application mapping to NoC processing elements operating at multiple voltage levels

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Performance and power efficient on-chip communication using adaptive virtual point-to-point connections

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
The Future of Formal Methods and GALS Design

Electronic Notes in Theoretical Computer Science (ENTCS)
Automated technique for design of NoC with minimal communication latency

CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Custom networks-on-chip architectures with multicast routing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A methodology for constraint-driven synthesis of on-chip communications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A system-level design methodology for application-specific networks-on-chip

Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Throughput-oriented NoC topology generation and analysis for high performance SoCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints

Proceedings of the 2010 ACM Symposium on Applied Computing
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
CAPPS: a framework for power-performance tradeoffs in bus-matrix-based on-chip communication architecture synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy efficient mapping and voltage islanding for regular NoC under design constraints

International Journal of High Performance Systems Architecture
Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network

Proceedings of the Conference on Design, Automation and Test in Europe
A holistic approach to network-on-chip synthesis

CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Floorplanning and topology generation for application-specific network-on-chip

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs

Journal of Systems Architecture: the EUROMICRO Journal
An efficient energy- and bandwidth- aware mapping algorithm for regular NoC architecture

Proceedings of the Third International Workshop on Network on Chip Architectures
Topology synthesis for low power cascaded crossbar switches

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans

International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
Design of network-on-chip architectures with a genetic algorithm-based technique

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Multi-objective topology synthesis and FPGA prototyping framework of application specific network-on-chip

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Cluster-based application mapping method for Network-on-Chip

Advances in Engineering Software
A tree-based topology synthesis for on-chip network

Proceedings of the International Conference on Computer-Aided Design
Voltage island-driven power optimization for application specific network-on-chip design

Proceedings of the great lakes symposium on VLSI
A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands

Integration, the VLSI Journal
A multi-objective mapping strategy for application specific emesh network-on-chip (noc)

ICSI'12 Proceedings of the Third international conference on Advances in Swarm Intelligence - Volume Part I
A survey on application mapping strategies for Network-on-Chip design

Journal of Systems Architecture: the EUROMICRO Journal
UNISM: unified scheduling and mapping for general networks on chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CusNoC: fast full-chip custom NoC generation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application-Specific Network-on-Chip synthesis with flexible router Placement

Journal of Systems Architecture: the EUROMICRO Journal
Power consumption of 3D networks-on-chips: Modeling and optimization

Microprocessors & Microsystems
High performance NoC synthesis using analytical modeling and simulation with optimal power and minimal IC area

Journal of Systems Architecture: the EUROMICRO Journal
Energy and buffer aware application mapping for networks-on-chip with self similar traffic

Journal of Systems Architecture: the EUROMICRO Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

Application-specific system-on-chip (SoC) design offers the opportunity for incorporating custom network-on-chip (NoC) architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents novel mixed integer linear programming (MILP) formulations for synthesis of custom NoC architectures. The optimization objective of the techniques is to minimize the power consumption subject to the performance constraints. We present a two-stage approach for solving the custom NoC synthesis problem. The power consumption of the NoC architecture is determined by both the physical links and routers. The power consumption of a physical link is dependent upon the length of the link, which in turn, is governed by the layout of the SoC. Therefore, in the first stage, we address the floorplanning problem that determines the locations of the various cores and the routers. In the second stage, we utilize the floorplan from the first stage to generate topology of the NoC and the routes for the various traffic traces. We also present a clustering-based heuristic technique for the second stage to reduce the run times of the MILP formulation. We analyze the quality of the results and solution times of the proposed techniques by extensive experimentation with realistic benchmarks and comparisons with regular mesh-based NoC architectures.