A Note on the Complexity of Dijkstra's Algorithm for Graphs with Weighted Vertices
IEEE Transactions on Computers
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler Physical Compiler and Prime Time
Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler Physical Compiler and Prime Time
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors
IEEE Transactions on Computers
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Graph Theory: Modeling, Applications, and Algorithms
Graph Theory: Modeling, Applications, and Algorithms
Graph Theory and Its Applications, Second Edition (Discrete Mathematics and Its Applications)
Graph Theory and Its Applications, Second Edition (Discrete Mathematics and Its Applications)
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
IEEE Transactions on Computers
Analysis of Computer and Communication Networks
Analysis of Computer and Communication Networks
Power optimization for application-specific networks-on-chips: A topology-based approach
Microprocessors & Microsystems
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-chip support for NoC-based SoC debugging
IEEE Transactions on Circuits and Systems Part I: Regular Papers
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Application-specific 3D Network-on-Chip design using simulated allocation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Circuits and Systems Part I: Regular Papers
3D Integration for NoC-based SoC Architectures
3D Integration for NoC-based SoC Architectures
Algorithms and Parallel Computing
Algorithms and Parallel Computing
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Designing power-efficient Networks-on-Chips (NoCs) for 3D ICs has emerged as a promising solution for complex mobile and portable applications. The total power consumption of a 3D NoC design depends on the allocation of the Intellectual properties (IPs) to the different network routers and the number of Through Silicon Vias (TSVs) used in the design. In this paper, we introduce a new analytical model for the power consumption of 3D NoCs. This new model relies on graph-theoretic concepts and incorporates static and dynamic power in order to present a more accurate evaluation of 3D NoC power consumption. The proposed model utilizes Dijkstra's algorithm to find shortest path routing. It also reflects the impact of using TSVs in 3D ICs. Using the proposed model, we develop a new methodology to select the 3D NoC topology and find the best IP-mapping. The proposed methodology utilizes a bio-inspired optimization technique. We compare particle swarm optimization (PSO) to genetic algorithms (GAs) in order to find the best 3D mesh network mapping that achieves minimum power consumption. The presented methodology is validated through two case studies to address symmetric and asymmetric multicore applications.