Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Design for Debug: Catching Design Errors in Digital Chips
IEEE Design & Test
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
IEEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Core-Based Scan Architecture for Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
An event-based monitoring service for networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Transaction-Based Communication-Centric Debug
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Design of Test Access Mechanism for AMBA-Based System-on-a-Chip
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
A multi-core debug platform for NoC-based systems
Proceedings of the conference on Design, automation and test in Europe
Functional Debug Techniques for Embedded Systems
IEEE Design & Test
A decorrelating design-for-digital-testability scheme for Σ-Δ modulators
IEEE Transactions on Circuits and Systems Part I: Regular Papers
An efficient SoC test technique by reusing on/off-chip bus bridge
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Functional post-silicon diagnosis and debug for networks-on-chip
Proceedings of the International Conference on Computer-Aided Design
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Power consumption of 3D networks-on-chips: Modeling and optimization
Microprocessors & Microsystems
Post-silicon platform for the functional diagnosis and debug of networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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This paper presents a design-for-debug (DfD) technique for network-on-chip (NoC)-based system-on-chips (SoCs). We present a test wrapper and, a test and debug interface unit. They enable data transfer between a tester/debugger and a core-under-test (CUT) or -debug (CUD) through the available NoC to facilitate test and debug. We also present a novel core debug supporting logic to enable transaction- and scan-based debug operations. The basic operations supported by our scheme include event processing, stop/run/single-step and selective storage of debug information such as current state, time, and debug event indication. This allows internal visibility and control into core operations. Experimental results show that single and multiple stepping through transactions are feasible with moderately low area overhead.