On reliable modular testing with vulnerable test access mechanisms
Proceedings of the 45th annual Design Automation Conference
Re-examining the use of network-on-chip as test access mechanism
Proceedings of the conference on Design, automation and test in Europe
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
IEICE - Transactions on Information and Systems
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism
Journal of Electronic Testing: Theory and Applications
On-chip support for NoC-based SoC debugging
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Test pin count reduction for NoC-based test delivery in multicore SOCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, two wrapper designs are proposed for core-based test application based on Networks-on-Chip (NoC) reuse. It will be shown that the previously proposed NoC wrapper does not efficiently utilize the NoC bandwidth, which may result in poor test schedules. Our wrappers (Type 1 and Type 2) complement each other to overcome this inefficiency while minimizing the overhead. The Type 2 wrapper uses larger area overhead to increase bandwidth efficiency, while the Type 1 takes advantage of some special configurations which may not require a complex and high-cost wrapper. Two wrapper optimization algorithms are applied to both wrapper designs under channel bandwidth and test time constraints, resulting in very little or no increase in the test application time compared to conventional TAM approaches.