Complexity and Approximation: Combinatorial Optimization Problems and Their Approximability Properties
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
The Impact of NoC Reuse on the Testing of Core-based Systems
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Test Scheduling for Network-on-Chip with BIST and Precedence Constraints
ITC '04 Proceedings of the International Test Conference on International Test Conference
Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints
ETS '07 Proceedings of the 12th IEEE European Test Symposium
DfT for the Reuse of Networks-on-Chip as Test Access Mechanism
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Time-Division-Multiplexed Test Delivery for NoC Systems
IEEE Design & Test
Improving the Test of NoC-Based SoCs with Help of Compression Schemes
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism
ETS '08 Proceedings of the 2008 13th European Test Symposium
Structural Test for Graceful Degradation of NoC Switches
ETS '11 Proceedings of the 2011 Sixteenth IEEE European Test Symposium
Constraint-Driven Test Scheduling for NoC-Based Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present the first pin-count-aware optimization approach for test data delivery over a network-on-chip (NoC). By co-optimizing core test scheduling and pin assignment to access points, the limited I/O resources provided by automated test equipment (ATE) can be used more effectively. This approach allows us to lower test cost by reducing test time for a given pin budget, or by reducing the number of test pins without impacting test time. To further improve resource utilization, we consider the use of MISRs for compacting the test responses of embedded cores. Experimental results for ITC'02 test benchmarks demonstrate that pin-count-aware co-optimization leads to shorter test times for a given pin-count budget and fewer pins for a given test-time budget. The results also highlight the advantages of the proposed use of output compaction.