Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism
Journal of Electronic Testing: Theory and Applications
A TDM slot allocation flow based on multipath routing in NoCs
Microprocessors & Microsystems
A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms
Journal of Parallel and Distributed Computing
Test pin count reduction for NoC-based test delivery in multicore SOCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Much current research has focused on employing networks on chips (NoCs) for communication among numerous cores on large-scale SoCs. One side benefit of such designs is the potential to use this communication infrastructure with little modification for manufacturing test delivery. This article presents a test-scheduling approach for such designs that minimizes test time through high-speed test delivery over the network and lower-rate test execution at the target cores. To achieve this, the authors interleave test data over the network via time-division multiplexing (TDM). To demonstrate the utility of this approach, they present a test-scheduling algorithm and a simulated test case from ITC 2002 SoC benchmarks. The results show significant test time and I/O savings when compared to a single-clock approach.