A simple approximation to minimum-delay routing
Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Theoretical Improvements in Algorithmic Efficiency for Network Flow Problems
Journal of the ACM (JACM)
Analysis of multi-path routing
IEEE/ACM Transactions on Networking (TON)
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
aSOC: A Scalable, Single-Chip Communications Architecture
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Interconnect intellectual property for network-on-chip (NoC)
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Big Omicron and big Omega and big Theta
ACM SIGACT News
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip
Proceedings of the 43rd annual Design Automation Conference
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
On the longest increasing subsequence of a circular list
Information Processing Letters
Online resource management in a multiprocessor with a network-on-chip
Proceedings of the 2007 ACM symposium on Applied computing
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Time-Division-Multiplexed Test Delivery for NoC Systems
IEEE Design & Test
A new selection policy for adaptive routing in network on chip
EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
TDM virtual-circuit configuration for network-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The aethereal network on chip after ten years: goals, evolution, lessons, and future
Proceedings of the 47th Design Automation Conference
Deadlock prevention in the ÆTHEREAL protocol
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Online allocation for contention-free-routing NoCs
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A TDM NoC supporting QoS, multicast, and fast connection set-up
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Providing multiple hard latency and throughput guarantees for packet switching networks on chip
Computers and Electrical Engineering
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Networks-on-chip have evolved as the natural solution for a scalable interconnect that can be automatically generated to suit the needs of the desired application. In this study we focus on improving the efficiency of on-chip networks using alternative routing strategies. We focus on a multi-path slot allocation method in networks with static resource reservations, in particular TDM NoCs. The simplicity of these networks makes it possible to implement this routing scheme without significant hardware overhead. Our proposed method, although displaying large variations between test cases, provides significant overall gains in terms of increased bandwidth or reduced working frequency or area. Our tests show that when using multipath routing the same communication requirements can be mapped on networks working on average at frequencies lower by 24.55% on average, while in individual cases the largest reduction was 60.04%. At the same time we are avoiding problems like deadlock and out-of-order delivery, commonly associated with multipath routing.