Real-Time Systems: Design Principles for Distributed Embedded Applications
Real-Time Systems: Design Principles for Distributed Embedded Applications
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Composable Resource Sharing Based on Latency-Rate Servers
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
aelite: a flit-synchronous network on chip with composable and predictable services
Proceedings of the Conference on Design, Automation and Test in Europe
Switch allocator for bufferless network-on-chip routers
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Design and implementation of an operating system for composable processor sharing
Microprocessors & Microsystems
A TDM slot allocation flow based on multipath routing in NoCs
Microprocessors & Microsystems
A minimalist cache coherent MPSoC designed for FPGAs
International Journal of High Performance Systems Architecture
Composable local memory organisation for streaming applications on embedded MPSoCs
Proceedings of the 8th ACM International Conference on Computing Frontiers
Time-predictable and composable architectures for dependable embedded systems
EMSOFT '11 Proceedings of the ninth ACM international conference on Embedded software
Online allocation for contention-free-routing NoCs
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
Concurrent hybrid switching for massively parallel systems-on-chip: the CYBER architecture
Proceedings of the 9th conference on Computing Frontiers
A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Static routing in symmetric real-time network-on-chips
Proceedings of the 20th International Conference on Real-Time and Network Systems
Microprocessors & Microsystems
An area-efficient network interface for a TDM-based network-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Proactive circuit allocation in multiplane NoCs
Proceedings of the 50th Annual Design Automation Conference
Designing energy-efficient NoC for real-time embedded systems through slack optimization
Proceedings of the 50th Annual Design Automation Conference
A TDM NoC supporting QoS, multicast, and fast connection set-up
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Ordering circuit establishment in multiplane NoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
The CompSOC design flow for virtual execution platforms
Proceedings of the 10th FPGAworld Conference
Proceedings of the Workshop on Embedded and Cyber-Physical Systems Education
Journal of Systems Architecture: the EUROMICRO Journal
A Unified WCET analysis framework for multicore platforms
ACM Transactions on Embedded Computing Systems (TECS)
Static analysis of multi-core TDMA resource arbitration delays
Real-Time Systems
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The goals for the Æthereal network on silicon, as it was then called, were set in 2000 and its concepts were defined early 2001. Ten years on, what has been achieved? Did we meet the goals, and what is left of the concepts? In this paper we answer those questions, and evaluate different implementations, based on a new performance: cost analysis. We discuss and reflect on our experiences, and conclude with open issues and future directions.