Microc/OS-II
Embedded Software Development with eCos
Embedded Software Development with eCos
Real-Time Virtual Resource: A Timely Abstraction for Embedded Systems
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Integrating Multimedia Applications in Hard Real-Time Systems
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Periodic Resource Model for Compositional Real-Time Guarantees
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Real Time Scheduling Theory: A Historical Perspective
Real-Time Systems
On-chip digital power supply control for system-on-chip applications
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Trading End-to-End Latency for Composability
RTSS '05 Proceedings of the 26th IEEE International Real-Time Systems Symposium
METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors
RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Multiprocessor resource allocation for throughput-constrained synchronous dataflow graphs
Proceedings of the 44th annual Design Automation Conference
Predator: a predictable SDRAM memory controller
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
IEEE Micro
Predictable programming on a precision timed architecture
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Composable Resource Sharing Based on Latency-Rate Servers
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
ISORC '10 Proceedings of the 2010 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing
The aethereal network on chip after ten years: goals, evolution, lessons, and future
Proceedings of the 47th Design Automation Conference
Worst-case response time analysis of resource access models in multi-core systems
Proceedings of the 47th Design Automation Conference
The OKL4 microvisor: convergence point of microkernels and hypervisors
Proceedings of the first ACM asia-pacific workshop on Workshop on systems
A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Design and implementation of an operating system for composable processor sharing
Microprocessors & Microsystems
On line power optimization of data flow multi-core architecture based on vdd-hopping for local DVFS
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Real-Time Systems: Design Principles for Distributed Embedded Applications
Real-Time Systems: Design Principles for Distributed Embedded Applications
Resource-Efficient Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration
RTCSA '11 Proceedings of the 2011 IEEE17th International Conference on Embedded and Real-Time Computing Systems and Applications - Volume 01
Automatic Generation of Efficient Predictable Memory Patterns
RTCSA '11 Proceedings of the 2011 IEEE17th International Conference on Embedded and Real-Time Computing Systems and Applications - Volume 01
A Unified Execution Model for Data-Driven Applications on a Composable MPSoC
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Independently-Developed Real-Time Systems on Multi-cores with Shared Resources
ECRTS '11 Proceedings of the 2011 23rd Euromicro Conference on Real-Time Systems
A new data flow analysis model for TDM
Proceedings of the tenth ACM international conference on Embedded software
Proceedings of the Workshop on Embedded and Cyber-Physical Systems Education
A reconfigurable real-time SDRAM controller for mixed time-criticality systems
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
| Hi-index | 0.00 |
Systems on chip (SOC) contain multiple concurrent applications with different time criticality (firm, soft, non real-time). As a result, they are often developed by different teams or companies, with different models of computation (MOC) such as dataflow, Kahn process networks (KPN), or time-triggered (TT). SOC functionality and (real-time) performance is verified after all applications have been integrated. In this paper we propose the CompSOC platform and design flows that offers a virtual execution platform per application, to allow independent design, verification, and execution. We introduce the composability and predictability concepts, why they help, and how they are implemented in the different resources of the CompSOC architecture. We define a design flow that allows real-time cyclo-static dataflow (CSDF) applications to be automatically mapped, verified, and executed. Mapping and analysis of KPN and TT applications is not automated but they do run composably in their allocated virtual platforms. Although most of the techniques used here have been published in isolation, this paper is the first comprehensive overview of the CompSOC approach. Moreover, three new case studies illustrate all claimed benefits: 1) An example firm-real-time CSDF H.263 decoder is automatically mapped and verified. 2) Applications with different models of computation (CSDF and TT) run composably. 3) Adaptive soft-real-time applications execute composably and can hence be verified independently by simulation.