The Evolving Philosophers Problem: Dynamic Change Management
IEEE Transactions on Software Engineering
Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
Real-Time Virtual Resource: A Timely Abstraction for Embedded Systems
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Proceedings of the 43rd annual Design Automation Conference
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
Scheduling multiple independent hard-real-time jobs on a heterogeneous multiprocessor
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Journal of Systems Architecture: the EUROMICRO Journal
Heterogeneous multi-core platform for consumer multimedia applications
Proceedings of the Conference on Design, Automation and Test in Europe
Resource adaptations with servers for hard real-time systems
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
Classification and Analysis of Predictable Memory Patterns
RTCSA '10 Proceedings of the 2010 IEEE 16th International Conference on Embedded and Real-Time Computing Systems and Applications
An improved algorithm for slot selection in the Æthereal network-on-chip
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
PRET DRAM controller: bank privatization for predictability and temporal isolation
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An Analyzable Memory Controller for Hard Real-Time CMPs
IEEE Embedded Systems Letters
PARDIS: a programmable memory controller for the DDRx interfacing standards
Proceedings of the 39th Annual International Symposium on Computer Architecture
Timing analysis of multi-mode applications on AUTOSAR conform multi-core systems
Proceedings of the Conference on Design, Automation and Test in Europe
Memory-map selection for firm real-time SDRAM controllers
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
RTAS '13 Proceedings of the 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)
| Hi-index | 0.00 |
Verifying real-time requirements of applications is increasingly complex on modern Systems-on-Chips (SoCs). More applications are integrated into one system due to power, area and cost constraints. Resource sharing makes their timing behavior interdependent, and as a result the verification complexity increases exponentially with the number of applications. Predictable and composable virtual platforms solve this problem by enabling verification in isolation, but designing SoC resources suitable to host such platforms is challenging. This paper focuses on a reconfigurable SDRAM controller for predictable and composable virtual platforms. The main contributions are: 1) A run-time reconfigurable SDRAM controller architecture, which allows trade-offs between guaranteed bandwidth, response time and power. 2) A methodology for offering composable service to memory clients, by means of composable memory patterns. 3) A reconfigurable Time-Division Multiplexing (TDM) arbiter and an associated reconfiguration protocol. The TDM slot allocations can be changed at run time, while the predictable and composable performance guarantees offered to active memory clients are unaffected by the reconfiguration. The SDRAM controller has been implemented as a TLM-level SystemC model, and in synthesizable VHDL for use on an FPGA.