An improved algorithm for slot selection in the Æthereal network-on-chip

Authors:
Radu Stefan;Kees Goossens
Affiliations:
Delft University of Technology;Eindhoven University of Technology
Venue:
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Year:
2011

Citing 12
Cited 2

Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
Networks on Chips: A New SoC Paradigm

Computer
Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels

IEEE Transactions on Parallel and Distributed Systems
aSOC: A Scalable, Single-Chip Communications Architecture

PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip

Proceedings of the conference on Design, automation and test in Europe - Volume 2
Interconnect intellectual property for network-on-chip (NoC)

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
DyAD: smart routing for networks-on-chip

Proceedings of the 41st annual Design Automation Conference
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Online resource management in a multiprocessor with a network-on-chip

Proceedings of the 2007 ACM symposium on Applied computing
A new selection policy for adaptive routing in network on chip

EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip

Journal of Systems Architecture: the EUROMICRO Journal
TDM virtual-circuit configuration for network-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Static routing in symmetric real-time network-on-chips

Proceedings of the 20th International Conference on Real-Time and Network Systems
A reconfigurable real-time SDRAM controller for mixed time-criticality systems

Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

Quantified Score

Hi-index	0.00

Visualization

Abstract

The rapid development in the electronics industry leads to a design process dominated by time-to-market constraints. The balance is shifted from logic design to packaging of already existing IP which results in a search for solutions for interconnecting the IP blocks. Networks-on-chip allow the rapid development a scalable interconnect and with the use of Circuit switching they can also provide guarantees for the speed of communication between IPs. In the current paper we demonstrate an improvement in the allocation algorithms for a Time-Division-Multiplexing Circuit-Switching scheme. We prove our algorithm to be optimal and we find that it provides an improvement of up to 26.7% compared to the previously proposed algorithm. The gain is more attractive as it comes at no cost for the actual hardware implementation.