Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations
Journal of VLSI Signal Processing Systems
Proceedings of the 2004 international workshop on System level interconnect prediction
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Distributed Multimedia System Design: A Holistic Perspective
Proceedings of the conference on Design, automation and test in Europe - Volume 2
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor
Proceedings of the 31st annual international symposium on Computer architecture
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
An architecture exploration environment for system on chip design
Nordic Journal of Computing
Design space exploration and prototyping for on-chip multimedia applications
Proceedings of the 43rd annual Design Automation Conference
Ant colony based routing architecture for minimizing hot spots in NOCs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
A design methodology for application-specific networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Proceedings of the 2007 ACM symposium on Applied computing
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A predictive NoC architecture for vision systems dedicated to image analysis
EURASIP Journal on Embedded Systems
Trends toward on-chip networked microsystems
International Journal of High Performance Computing and Networking
An Efficient Implementation Method of Arbiter for the ML-AHB Busmatrix
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A generic adaptive path-based routing method for MPSoCs
Journal of Systems Architecture: the EUROMICRO Journal
An improved algorithm for slot selection in the Æthereal network-on-chip
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
A TDM slot allocation flow based on multipath routing in NoCs
Microprocessors & Microsystems
Virtualizing network-on-chip resources in chip-multiprocessors
Microprocessors & Microsystems
SONA: an on-chip network for scalable interconnection of AMBA-Based IPs
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part IV
Synchroscalar: initial lessons in power-aware design of a tile-based embedded architecture
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
A TDM NoC supporting QoS, multicast, and fast connection set-up
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Microprocessors & Microsystems
Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs
Microprocessors & Microsystems
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As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with on-chip system-level issues such as adaptability and scalability. Recent trends indicate that next generation systems will require new architectures and compilation tools that effectively deal with these constraints. In this paper, a new single-chip interconnect architecture, adaptive System-On-a-Chip, is described that not only provides scalable data transfer, but also can be easily reconfigured as application-level communication patterns change. An important aspect of the architecture is its support for compile-time, scheduled communication. To illustrate the benefits of the architecture, three DSP benchmarks have been mapped to candidate SoC devices of assorted sizes, which contain the new, interconnect architecture. The described interconnect architecture is shown to be up to 5 times more efficient than bus-based SoC interconnect architectures via parallel simulation. Additionally, a preliminary layout of our architecture is shown and derived area and performance parameters are presented.