Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
aSOC: A Scalable, Single-Chip Communications Architecture
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Guaranteeing the quality of services in networks on chip
Networks on chip
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
An event-based monitoring service for networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Mapping and configuration methods for multi-use-case networks on chips
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Application-specific network-on-chip architecture customization via long-range link insertion
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Networks on chips for high-end consumer-electronics TV system architectures
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Efficient link capacity and QoS design for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Efficient space-time noc path allocation based on mutual exclusion and pre-reservation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Fast, Accurate and Detailed NoC Simulations
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Proceedings of the conference on Design, automation and test in Europe
Routing table minimization for irregular mesh NoCs
Proceedings of the conference on Design, automation and test in Europe
Congestion-controlled best-effort communication for networks-on-chip
Proceedings of the conference on Design, automation and test in Europe
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A tool for automatic detection of deadlock in wormhole networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A monitoring-aware network-on-chip design flow
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Systems Architecture: the EUROMICRO Journal
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synthesis of networks on chips for 3D systems on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A platform-based design framework for joint SW/HW multiprocessor systems design
Journal of Systems Architecture: the EUROMICRO Journal
The era of many-modules SoC: revisiting the NoC mapping problem
Proceedings of the 2nd International Workshop on Network on Chip Architectures
A networks-on-chip architecture design space exploration - The LIB
Computers and Electrical Engineering
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Node resource management for DSP applications on 3D network-on-chip architecture
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
ACM Transactions on Embedded Computing Systems (TECS)
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism
Journal of Electronic Testing: Theory and Applications
Leveraging application-level requirements in the design of a NoC for a 4G SoC: a case study
Proceedings of the Conference on Design, Automation and Test in Europe
A high-level debug environment for communication-centric debug
Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Real-Time Image Processing
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implementation of QoSS (quality-of-security service) for NoC-based SoC protection
Transactions on computational science X
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Analytical derivation of traffic patterns in cache-coherent shared-memory systems
Microprocessors & Microsystems
Handling global traffic in future CMP NoCs
Proceedings of the International Workshop on System Level Interconnect Prediction
An automatic design flow for mapping application onto a 2D mesh NoC architecture
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
A divide and conquer based distributed run-time mapping methodology for many-core platforms
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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Systems on chip (SOC) are composed of intellectual property blocks (IP) and interconnect. While mature tooling exists to design the former, tooling for interconnect design is still a research area. In this paper we describe an operational design flow that generates and configures application-specific network on chip (NOC) instances, given application communication requirements. The NOC can be simulated in SystemC and RTL VHDL. An independent performance verification tool verifies analytically that the NOC instance (hardware) and its configuration (software) together meet the application performance requirements. The 脝thereal NOC's guaranteed performance is essential to replace time-consuming simulation by fast analytical performance validation. As a result, application-specific NOCs that are guaranteed to meet the application's communication requirements are generated and verified in minutes, reducing the number of design iterations. A realistic MPEG SOC example substantiates our claims.