A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Models for Embedded Application Mapping onto NoCs: Timing Analysis
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Mapping and configuration methods for multi-use-case networks on chips
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Networks on chips for high-end consumer-electronics TV system architectures
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Hi-index | 0.00 |
This paper focuses on efficient deployment of real applications over an ad hoc NoC. We propose a methodology and a tool to decide the NoC parameters and to generate the path coding within network interfaces for guarantied and best effort communications. The originality of our approach is based on two points. First, we take advantage of mutual exclusive communications. Secondly, our path allocation technique increases success opportunity and reduce buffer cost thanks to a pre-reservation step while taking into account mutual exclusions. We present real implementations for a smart camera application and a 4G telecom scheme.