Quality of service based routing: a performance perspective
Proceedings of the ACM SIGCOMM '98 conference on Applications, technologies, architectures, and protocols for computer communication
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Interconnection Networks for Multiprocessors and Multicomputers: Theory and Practice
Interconnection Networks for Multiprocessors and Multicomputers: Theory and Practice
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Complete Network-On-Chip Emulation Framework
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An event-based monitoring service for networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MAIA: a framework for networks on chip generation and verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
A monitoring-aware network-on-chip design flow
Journal of Systems Architecture: the EUROMICRO Journal
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A simplified executable model to evaluate latency and throughput of networks-on-chip
Proceedings of the 21st annual symposium on Integrated circuits and system design
Long-range dependence and on-chip processor traffic
Microprocessors & Microsystems
Flexible and abstract communication and interconnect modeling for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A flexible framework for communication evaluation in SoC design
International Journal of Parallel Programming
Polaris: a system-level roadmapping toolchain for on-chip interconnection networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Embedded Computing Systems (TECS)
An analytical method for evaluating network-on-chip performance
Proceedings of the Conference on Design, Automation and Test in Europe
Comprehensive on-chip traffic generator model for SoC design and synthesis
SpringSim '10 Proceedings of the 2010 Spring Simulation Multiconference
Static timing analysis for modeling QoS in networks-on-chip
Journal of Parallel and Distributed Computing
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
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A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency and throughput). In this paper we present a simulation-based approach to address this problem. We use XML to instantiate network components (routers, network interfaces) and their composition. NoCs are evaluated in terms of cost and performance by sweeping over different parameters (e.g. network topology, network interface queue depth). We then show, how we can obtain trade-off plots by using the results obtained with our simulation environment. Finally,by means of two examples we illustrate how trade-off plots can help the NoC designers in selecting the right network based on a set of different constraints.