On the self-similar nature of Ethernet traffic (extended version)
IEEE/ACM Transactions on Networking (TON)
Mathematics handbook for science and engineering
Mathematics handbook for science and engineering
Theory of Modeling and Simulation
Theory of Modeling and Simulation
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Prediction-based flow control for network-on-chip traffic
Proceedings of the 43rd annual Design Automation Conference
Application driven traffic modeling for NoCs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
A Statistical Traffic Model for On-Chip Interconnection Networks
MASCOTS '06 Proceedings of the 14th IEEE International Symposium on Modeling, Analysis, and Simulation
A Generic Multi-Phase On-Chip Traffic Generation Environment
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Automatic phase detection for stochastic on-chip traffic generation
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Adaptive aggregation on chip multiprocessors
VLDB '07 Proceedings of the 33rd international conference on Very large data bases
| Hi-index | 0.00 |
On-Chip traffic Modeling is a new research topic that came along with Network on Chip (NoC) design. On-chip traffic varies in rate and nature depending on the running application and the System on Chip components. Different traffic models have been proposed as an attempt to capture the various transactions that occur inside the NoC, which connects different Intellectual Properties (IPs) on the same chip. In this research paper, recent traffic modeling paradigms will be reviewed and discussed. These models have been developed into traffic generator entities to emulate the traffic patterns on chip. However, none of these models (and hence traffic generators) completely capture the behavior of different applications and the interactions between different IPs components on chip, which can alter the traffic state and rate. In this paper, we will propose a comprehensive and flexible model that is based on Discrete EVent System Specification formalisms (DEVS) for modeling and simulation. Our model could be implemented as a traffic generator that has three internal functions, and input and output ports for the interactions with other IPs components such as caches, DSP units, etc.