Towards Open Network-on-Chip Benchmarks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Low-Cost VC Allocator Design for Virtual Channel Wormhole Routers in Networks-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Polaris: a system-level roadmapping toolchain for on-chip interconnection networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Triplet-based topology for on-chip networks
WSEAS Transactions on Computers
Applying network calculus for performance analysis of self-similar traffic in on-chip networks
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Statistical physics approaches for network-on-chip traffic characterization
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Hybrid network on chip (HNoC): local buses with a global mesh architecture
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Group-caching for NoC based multicore cache coherent systems
Proceedings of the Conference on Design, Automation and Test in Europe
Comprehensive on-chip traffic generator model for SoC design and synthesis
SpringSim '10 Proceedings of the 2010 Spring Simulation Multiconference
Workload characterization and its impact on multicore platform design
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ERA: an efficient routing algorithm for power, throughput and latency in network-on-chips
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
A framework for designing congestion-aware deterministic routing
Proceedings of the Third International Workshop on Network on Chip Architectures
A hardwired NoC infrastructure for embedded systems on FPGAs
Microprocessors & Microsystems
Inferring packet dependencies to improve trace based simulation of on-chip networks
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Abstraction-based performance verification of NoCs
Proceedings of the 48th Design Automation Conference
Capacity optimized NoC for multi-mode SoC
Proceedings of the 48th Design Automation Conference
Floodgate: application-driven flow control in network-on-chip for many-core architectures
Proceedings of the 4th International Workshop on Network on Chip Architectures
Network-on-chip traffic modeling for data flow applications
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
International Journal of Embedded and Real-Time Communication Systems
Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys (CSUR)
An analytical latency model for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A synthetic task model for HPC-grade optical network performance evaluation
IA^3 '13 Proceedings of the 3rd Workshop on Irregular Applications: Architectures and Algorithms
TornadoNoC: A lightweight and scalable on-chip network architecture for the many-core era
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the International Conference on Computer-Aided Design
Energy and buffer aware application mapping for networks-on-chip with self similar traffic
Journal of Systems Architecture: the EUROMICRO Journal
A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure
Computers and Electrical Engineering
Systolic traffic modelling in network on chip
International Journal of Wireless and Mobile Computing
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Network traffic modeling is a critical first step towards understanding and unraveling network power/performancerelated issues. Extensive prior research in the area of classic networks such as the Internet, Ethernet, and wireless LANs transporting TCP/IP, HTTP, and FTP traffic among others, has demonstrated how traffic models and model-based synthetic traffic generators can facilitate understanding of traffic characteristics and drive early-stage simulation to explore a large network design space. Though on-chip networks (a.k.a networks-on-chip (NoCs)) are becoming the de-facto scalable communication fabric in many-core systems-on-a-chip (SoCs) and chip multiprocessors (CMPs), no on-chip network traffic model that captures both spatial and temporal variations of traffic has been demonstrated yet. As available on-chip resources increase with technology scaling, enabling a myriad of new network architectures, NoCs need to be designed from the application's perspective. In this paper we propose such an empirically-derived network on-chip traffic model for homogeneous NoCs. Our comprehensive model is based on three statistical parameters described with a 3-tuple, and captures the spatio-temporal characteristics of NoC traffic accurately with less than 5% error when compared to actual NoC application traces gathered from fullsystem simulations of three different chip platforms. We illustrate two potential uses of our traffic model: how it allows us to characterize and gain insights on NoC traffic patterns, and how it can be used to generate synthetic traffic traces that can drive NoC design-space exploration.