Steady-state simulation of queueing processes: survey of problems and solutions
ACM Computing Surveys (CSUR)
The Markov-modulated Poisson process (MMPP) cookbook
Performance Evaluation
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Hypercube Communication Delay with Wormhole Routing
IEEE Transactions on Computers
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Queueing Networks and Markov Chains
Queueing Networks and Markov Chains
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
A Statistical Traffic Model for On-Chip Interconnection Networks
MASCOTS '06 Proceedings of the 14th IEEE International Symposium on Modeling, Analysis, and Simulation
An accurate mathematical performance model of adaptive routing in the star graph
Future Generation Computer Systems
Caspian: A Tunable Performance Model for Multi-core Systems
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
Application Specific Routing Algorithms for Networks on Chip
IEEE Transactions on Parallel and Distributed Systems
A framework for designing congestion-aware deterministic routing
Proceedings of the Third International Workshop on Network on Chip Architectures
Buffer optimization in network-on-chip through flow regulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical approach for network-on-chip performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys (CSUR)
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the International Conference on Computer-Aided Design
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We propose an analytical model based on queueing theory for delay analysis in a wormhole-switched network-on-chip (NoC). The proposed model takes as input an application communication graph, a topology graph, a mapping vector, and a routing matrix, and estimates average packet latency and router blocking time. It works for arbitrary network topology with deterministic routing under arbitrary traffic patterns. This model can estimate per-flow average latency accurately and quickly, thus enabling fast design space exploration of various design parameters in NoC designs. Experimental results show that the proposed analytical model can predict the average packet latency more than four orders of magnitude faster than an accurate simulation, while the computation error is less than 10% in non-saturated networks for different system-on-chip platforms.