Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
Trust-region methods
Performance Guarantees in Communication Networks
Performance Guarantees in Communication Networks
Interior-Point Methods for Nonconvex Nonlinear Programming: Filter Methods and Merit Functions
Computational Optimization and Applications
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A basic stochastic network calculus
Proceedings of the 2006 conference on Applications, technologies, architectures, and protocols for computer communications
System architecture evaluation using modular performance analysis: a case study
International Journal on Software Tools for Technology Transfer (STTT)
Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
TDM virtual-circuit configuration for network-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PERMAP: A performance-aware mapping for application-specific SoCs
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
Networks-on-Chips: Theory and Practice
Networks-on-Chips: Theory and Practice
Network calculus: a theory of deterministic queuing systems for the internet
Network calculus: a theory of deterministic queuing systems for the internet
Optimal regulation of traffic flows in networks-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Flow regulation for on-chip communication
Proceedings of the Conference on Design, Automation and Test in Europe
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Streamlined network-on-chip for multicore embedded architectures
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys (CSUR)
An analytical latency model for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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For network-on-chip (NoC) designs, optimizing buffers is an essential task since buffers are a major source of cost and power consumption. This paper proposes flow regulation and has defined a regulation spectrum as a means for system-on-chip architects to control delay and backlog bounds. The regulation is performed per flow for its peak rate and burstiness. However, many flows may have conflicting regulation requirements due to interferences with each other. Based on the regulation spectrum, this paper optimizes the regulation parameters aiming for buffer optimization. Three timing-constrained buffer optimization problems are formulated, namely, buffer size minimization, buffer variance minimization, and multiobjective optimization, which has both buffer size and variance as minimization objectives. Minimizing buffer variance is also important because it affects the modularity of routers and network interfaces. A realistic case study exhibits 62.8% reduction of total buffers, 84.3% reduction of total latency, and 94.4% reduction on the sum of variances of buffers. Likewise, the experimental results demonstrate similar improvements in the case of synthetic traffic patterns. The optimization algorithm has low run-time complexity, enabling quick exploration of large design spaces. This paper concludes that optimal flow regulation can be a highly valuable instrument for buffer optimization in NoC designs.