Mathematical formalisms for performance evaluation of networks-on-chip

  • Authors:
  • Abbas Eslami Kiasari;Axel Jantsch;Zhonghai Lu

  • Affiliations:
  • KTH Royal Institute of Technology;KTH Royal Institute of Technology;KTH Royal Institute of Technology

  • Venue:
  • ACM Computing Surveys (CSUR)
  • Year:
  • 2013

Quantified Score

Hi-index 0.00

Visualization

Abstract

This article reviews four popular mathematical formalisms—queueing theory, network calculus, schedulability analysis, and dataflow analysis—and how they have been applied to the analysis of on-chip communication performance in Systems-on-Chip. The article discusses the basic concepts and results of each formalism and provides examples of how they have been used in Networks-on-Chip (NoCs) performance analysis. Also, the respective strengths and weaknesses of each technique and its suitability for a specific purpose are investigated. An open research issue is a unified analytical model for a comprehensive performance evaluation of NoCs. To this end, this article reviews the attempts that have been made to bridge these formalisms.