Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
Performance Guarantees in Communication Networks
Performance Guarantees in Communication Networks
Rational clocking [digital systems design]
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 2
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
System architecture evaluation using modular performance analysis: a case study
International Journal on Software Tools for Technology Transfer (STTT)
NoC design flow for TDMA and QoS management in a GALS context
EURASIP Journal on Embedded Systems
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
TDM virtual-circuit configuration for network-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multicore processing and efficient on-chip caching for H.264 and future video decoders
IEEE Transactions on Circuits and Systems for Video Technology
Analysis of worst-case delay bounds for on-chip packet-switching networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
aelite: a flit-synchronous network on chip with composable and predictable services
Proceedings of the Conference on Design, Automation and Test in Europe
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys (CSUR)
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We propose cross clock-domain time-division-multiplexing (TDM) Virtual Circuit (VC), in short, VC, to provide delay and bandwidth guaranteed communication for NoCs with multiple clock domains. The cross-domain VC extends the synchronous VC in a single clock domain to multiple clock domains. The synchronous VCs reserve cyclic time slots at each node from source to destination for a traffic flow to use shared links without contention based on the assumption that all nodes share the same notion of time. However, when VCs pass multiple clock domains with different phases and frequencies, the assumption of global synchrony is not valid any more and consequently they cannot function correctly. This paper addresses this problem based on a typical FIFO clock domain interface. We give the conditions and a realization scheme to ensure correct packet delivery with QoS for VCs crossing multiple clock domains. We apply network calculus to analyze and derive the bounds of the packet delay and the FIFO size.