Bus access optimization for distributed embedded systems based on schedulability analysis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Bounds on Maximum Delay in Networks with Deflection Routing
IEEE Transactions on Parallel and Distributed Systems
Deterministic Many-to-Many Hot Potato Routing
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
From 2D to 3D NoCs: a case study on worst-case communication performance
Proceedings of the 2009 International Conference on Computer-Aided Design
Analysis of worst-case delay bounds for on-chip packet-switching networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Flow regulation for on-chip communication
Proceedings of the Conference on Design, Automation and Test in Europe
Buffer optimization in network-on-chip through flow regulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An improved algorithm for slot selection in the Æthereal network-on-chip
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
A TDM slot allocation flow based on multipath routing in NoCs
Microprocessors & Microsystems
Journal of Parallel and Distributed Computing
Cross clock-domain TDM virtual circuits for networks on chips
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Microprocessors & Microsystems
Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Static routing in symmetric real-time network-on-chips
Proceedings of the 20th International Conference on Real-Time and Network Systems
Providing multiple hard latency and throughput guarantees for packet switching networks on chip
Computers and Electrical Engineering
Microprocessors & Microsystems
| Hi-index | 0.00 |
In network-on-chip (NoC), time-division-multiplexing (TDM) virtual circuits (VCs) have been proposed to satisfy the quality-of-service requirements of applications. TDM VC is a connection-oriented communication service by which two or more connections take turns to share buffers and link bandwidth using dedicated time slots. In the paper, we first give a formulation of the multinode VC configuration problem for arbitrary NoC topologies. A multinode VC allows multiple source and destination nodes on it. Then we address the two problems of path selection and slot allocation for TDM VC configuration. For the path selection, we use a backtracking algorithm to explore the path diversity, constructively searching the solution space. In the slot allocation phase, overlapped VCs must be configured such that no conflict occurs and their bandwidth requirements are satisfied. We define the concept of a logical network (LN) as an infinite set of associated (time slot, buffer) pairs with respect to a buffer on a given VC. Based on this concept, we develop and prove theorems that constitute sufficient and necessary conditions to establish conflict-free VCs. They are applicable for networks where all nodes operate with the same clock frequency but allowing different phases. Using these theorems, slot allocation for VCs is a procedure of assigning VCs to different LNs. TDM VC configuration can thus be predictable and correct-by-construction. Our experiments on synthetic and real applications validate the effectiveness and efficiency of our approach.