Routing, merging, and sorting on parallel models of computation
Journal of Computer and System Sciences
Sharp approximation models of adaptive routing in mesh networks (preliminary report)
Proc. of the international seminar on Teletraffic analysis and computer performance evaluation
A framework for adaptive routing in multicomputer networks
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Deflection routing in certain regular networks
Deflection routing in certain regular networks
Bounds on evacuation time for deflection routing
Distributed Computing
Unslotted deflection routing: a practical and efficient protocol for multihop optical networks
IEEE/ACM Transactions on Networking (TON)
Õ(congestion + dilation) hot-potato routing on leveled networks
Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures
A Mixed Deflection and Convergence Routing Algorithm: Design and Performance
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
Evaluation of on-chip networks using deflection routing
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
The Data Vortex, an All Optical Path Multicomputer Interconnection Network
IEEE Transactions on Parallel and Distributed Systems
Efficient bufferless packet switching on trees and leveled networks
Journal of Parallel and Distributed Computing
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Analysis of communication delay bounds for network on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
TDM virtual-circuit configuration for network-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Convergence Routing under Bursty Traffic: Instability and an AIMD Controller
Electronic Notes in Theoretical Computer Science (ENTCS)
Analysis of worst-case delay bounds for on-chip packet-switching networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
WAOA'04 Proceedings of the Second international conference on Approximation and Online Algorithms
A scalable and fault-tolerant network routing scheme for many-core and multi-chip systems
Journal of Parallel and Distributed Computing
Efficient buffering and scheduling for a single-chip crosspoint-queued switch
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
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We consider the problem of finding the worst case packet transit delay in networks using deflection routing. Several classes of networks are studied, including many topologies for which deflection routing has been proposed or implemented (e.g., hypercube, Manhattan Street Network, shuffle-exchange network). We derive new upper bounds on the evacuation time of batch admissions, and present simple proofs for several existing bounds. Also derived are bounds on worst case transit delay for certain networks admitting packets continuously. To demonstrate the practical utility of our results, we compare a new delay bound to the maximum delay observed in simulations. The results have application in both protocol design and the determination of the required capacity of packet resequencing buffers.