A scalable and fault-tolerant network routing scheme for many-core and multi-chip systems

Authors:
Wen-Chung Tsai;Kuo-Chih Chu;Yu-Hen Hu;Sao-Jie Chen
Affiliations:
Information and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu 310, Taiwan, ROC;Department of Electronic Engineering, Lunghwa University of Science and Technology, Taoyuan 333, Taiwan, ROC;Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, WI 53706-1691, USA;Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan, ROC
Venue:
Journal of Parallel and Distributed Computing
Year:
2012

Citing 21
Cited 0

Deadlock-Free Message Routing in Multiprocessor Interconnection Networks

IEEE Transactions on Computers
The turn model for adaptive routing

Journal of the ACM (JACM)
The Chaos Router

IEEE Transactions on Computers
An efficient, fully adaptive deadlock recovery scheme: DISHA

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The Odd-Even Turn Model for Adaptive Routing

IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
Networks on Chips: A New SoC Paradigm

Computer
Bounds on Maximum Delay in Networks with Deflection Routing

IEEE Transactions on Parallel and Distributed Systems
Research Challenges for On-Chip Interconnection Networks

IEEE Micro
3-D topologies for networks-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

Proceedings of the 45th annual Design Automation Conference
An Efficient Implementation of Distributed Routing Algorithms for NoCs

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A case for bufferless routing in on-chip networks

Proceedings of the 36th annual international symposium on Computer architecture
Three-dimensional silicon integration

IBM Journal of Research and Development
HiRA: A methodology for deadlock free routing in hierarchical networks on chip

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Flexible DOR routing for virtualization of multicore chips

SOC'09 Proceedings of the 11th international conference on System-on-chip
Evaluating Bufferless Flow Control for On-chip Networks

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A highly resilient routing algorithm for fault-tolerant NoCs

Proceedings of the Conference on Design, Automation and Test in Europe
Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and Tori

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Autonet: a high-speed, self-configuring local area network using point-to-point links

IEEE Journal on Selected Areas in Communications

Quantified Score

Hi-index	0.00

Visualization

Abstract

Current on-chip network and inter-chip interconnection are designed separately. However, this traditional design methodology faces a great challenge: in a multi-chip system, each many-core chip contains hundreds or thousands of processors. The increasing number of on-chip processors must share one input/output unit to interface with the inter-chip interconnection. The increased network usage at the chip interface may create an uneven traffic load in the on-chip network. That is, traffic jams could occur in the chip area around the input/output unit. New technologies, such as through silicon via and silicon interposer, can directly connect networks on chips. These technologies can improve communication performance and reduce power consumption by omitting the input/output unit. This paper proposes a novel routing scheme to deal with the network scalability issues related to the many-core and multi-chip system-in-package paradigm. The proposed scheme can also enhance the fault-tolerance of nano-scale communication in deep-submicron designs.