The turn model for adaptive routing

A universal proof technique for deadlock-free routing in interconnection networks

Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures

ROMM routing on mesh and torus networks

Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures

A Flexible Bit-Pattern Associative Router for Interconnection Networks

IEEE Transactions on Parallel and Distributed Systems

A Traffic-Balanced Adaptive Wormhole Routing Scheme for Two-Dimensional Meshes

IEEE Transactions on Computers

Optimally adaptive, minimum-distance, circuit-switched routing in hypercubes

ACM Transactions on Computer Systems (TOCS)

System area network mapping

Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures

Triplex: a multi-class routing algorithm

Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures

Edge Congestion of Shortest Path Systems for All-to-All Communication

IEEE Transactions on Parallel and Distributed Systems

A General Theory for Deadlock Avoidance in Wormhole-Routed Networks

IEEE Transactions on Parallel and Distributed Systems

Wormhole routing techniques for directly connected multicomputer systems

ACM Computing Surveys (CSUR)

Adaptive-Trail Routing and Performance Evaluation in Irregular Networks Using Cut-Through Switches

IEEE Transactions on Parallel and Distributed Systems

The Odd-Even Turn Model for Adaptive Routing

IEEE Transactions on Parallel and Distributed Systems

On Load Balancing in Multicomputer/Distributed Systems Equipped with Circuit or Cut-Through Switching Capability

IEEE Transactions on Computers

Optimal Processor Mapping for Linear-Complement Communication on Hypercubes

IEEE Transactions on Parallel and Distributed Systems

A deterministic fault-tolerant and deadlock-free routing protocol in 2-D meshes based on odd-even turn model

ICS '02 Proceedings of the 16th international conference on Supercomputing

Performance tuning of adaptive wormhole routing through selection function choice

Journal of Parallel and Distributed Computing

Balancing Buffer Utilization in Meshes Using a 'Restricted Area' Concept

IEEE Transactions on Parallel and Distributed Systems

Comparative Analysis of Adaptive Wormhole Routing in Tori and Hypercubes in the Presence of Hotspot Traffic

IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium

A Simple Incremental Network Topology for Wormhole Switch-Based Networks

IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium

Deadlock Avoidance for Wormhole Based Switches

Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing

Adaptive Path-Based Multicast on Wormhole-Routed Hypercubes

Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing

Application of network calculus to general topologies using turn-prohibition

IEEE/ACM Transactions on Networking (TON)

A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model

IEEE Transactions on Computers

DyAD: smart routing for networks-on-chip

Proceedings of the 41st annual Design Automation Conference

Part II: A Methodology for Developing Deadlock-Free Dynamic Network Reconfiguration Processes

IEEE Transactions on Parallel and Distributed Systems

HERMES: an infrastructure for low area overhead packet-switching networks on chip

Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics

Virtual channels in networks on chip: implementation and evaluation on hermes NoC

SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design

Application-specific buffer space allocation for networks-on-chip router design

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

MAIA: a framework for networks on chip generation and verification

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

A survey of research and practices of Network-on-chip

ACM Computing Surveys (CSUR)

Computation and communication refinement for multiprocessor SoC design: A system-level perspective

Proceedings of the 41st annual Design Automation Conference

DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip

Proceedings of the 43rd annual Design Automation Conference

Increasing the throughput of an adaptive router in network-on-chip (NoC)

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

A methodology for design of application specific deadlock-free routing algorithms for NoC systems

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

Deadlock-free connection-based adaptive routing with dynamic virtual circuits

Journal of Parallel and Distributed Computing

A deadlock detection mechanism for true fully adaptive routing in regular wormhole networks

Computer Communications

Architecture of the Scalable Communications Core

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip

An optimal scheduling algorithm for an agent-based multicast strategy on irregular networks

The Journal of Supercomputing

Architecture of the Scalable Communications Core's Network on Chip

IEEE Micro

Dynamic channel selection: an efficient strategy for balancing traffic in meshes

International Journal of Computational Science and Engineering

A new selection policy for adaptive routing in network on chip

EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications

Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions

Journal of Systems Architecture: the EUROMICRO Journal

An empirical performance analysis of minimal and non-minimal routing in cube-based OTIS multicomputers

Journal of High Speed Networks

Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip

BARP-a dynamic routing protocol for balanced distribution of traffic in NoCs

Proceedings of the conference on Design, automation and test in Europe

Efficient Deadlock Detection in Parallel Computer Systems with Wormhole Routing

ICCS '07 Proceedings of the 7th international conference on Computational Science, Part I: ICCS 2007

Deadlock-Free Adaptive Routing in 2D Tori with a New Turn Model

ICA3PP '08 Proceedings of the 8th international conference on Algorithms and Architectures for Parallel Processing

Unicast-based fault-tolerant multicasting in wormhole-routed hypercubes

Journal of Systems Architecture: the EUROMICRO Journal

A voltage-frequency island aware energy optimization framework for networks-on-chip

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Application-aware deadlock-free oblivious routing

Proceedings of the 36th annual international symposium on Computer architecture

Static virtual channel allocation in oblivious routing

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip

An Advanced NoP Selection Strategy for Odd-Even Routing Algorithm in Network-on-Chip

ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing

Region-based routing: a mechanism to support efficient routing algorithms in NoCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Path-based, randomized, oblivious, minimal routing

Proceedings of the 2nd International Workshop on Network on Chip Architectures

A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures

Computers and Electrical Engineering

Balancing traffic in meshes by dynamic channel selection

ISPA'03 Proceedings of the 2003 international conference on Parallel and distributed processing and applications

A routing methodology for dynamic fault tolerance in meshes and tori

HiPC'07 Proceedings of the 14th international conference on High performance computing

Design of a router for network-on-chip

International Journal of High Performance Systems Architecture

EDXY - A low cost congestion-aware routing algorithm for network-on-chips

Journal of Systems Architecture: the EUROMICRO Journal

An insertion loss balance aware routing scheme in photonic network on chip

ICICS'09 Proceedings of the 7th international conference on Information, communications and signal processing

Quarter Load Threshold (QLT) flow control for wormhole switching in mesh-based Network-on-Chip

Journal of Systems Architecture: the EUROMICRO Journal

Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip

SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design

A framework for designing congestion-aware deterministic routing

Proceedings of the Third International Workshop on Network on Chip Architectures

iFDOR: dynamic rerouting on-chip

Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip

Automatic verification for deadlock in Networks-on-Chips with adaptive routing and wormhole switching

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Tree-turn routing: an efficient deadlock-free routing algorithm for irregular networks

The Journal of Supercomputing

On the influence of the selection function on the performance of fat-trees

Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing

Network-on-Chip routing algorithms by breaking cycles

ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I

TransCom: transforming stream communication for load balance and efficiency in networks-on-chip

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

A method for router table compression for application specific routing in mesh topology noc architectures

SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation

An optimal scheduling algorithm for an agent-based multicast strategy on irregular networks

GPC'06 Proceedings of the First international conference on Advances in Grid and Pervasive Computing

A simple and efficient input selection function for networks-on-chip

ICDCN'12 Proceedings of the 13th international conference on Distributed Computing and Networking

Networks on chips: structure and design methodologies

Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies

A scalable and fault-tolerant network routing scheme for many-core and multi-chip systems

Journal of Parallel and Distributed Computing

An efficient routing methodology to tolerate static and dynamic faults in 2-D mesh networks-on-chip

Microprocessors & Microsystems

An automatic design flow for mapping application onto a 2D mesh NoC architecture

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation

Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips

Proceedings of the Fifth International Workshop on Network on Chip Architectures

Developing Domain-Knowledge Evolutionary Algorithms for Network-on-Chip Application Mapping

Microprocessors & Microsystems

Enabling power efficiency through dynamic rerouting on-chip

ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures

Non-minimal, turn-model based NoC routing

Microprocessors & Microsystems