Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches
IEEE Transactions on Computers
The turn model for adaptive routing
Journal of the ACM (JACM)
Asynchronous transfer mode (3rd ed.): solution for broadband ISDN
Asynchronous transfer mode (3rd ed.): solution for broadband ISDN
An efficient, fully adaptive deadlock recovery scheme: DISHA
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
IEEE Transactions on Parallel and Distributed Systems
Compressionless Routing: A Framework for Adaptive and Fault-Tolerant Routing
IEEE Transactions on Parallel and Distributed Systems
The Case for Chaotic Adaptive Routing
IEEE Transactions on Computers
Supporting systolic and memory communication in iWarp
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Performance evaluation of a new routing strategy for irregular networks with source routing
Proceedings of the 14th international conference on Supercomputing
Communications of the ACM
Spider: A High-Speed Network Interconnect
IEEE Micro
IEEE Transactions on Parallel and Distributed Systems
Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels
IEEE Transactions on Parallel and Distributed Systems
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks
HPCA '97 Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture
Comparative Study on Restoration Schemes of Survivable ATM Networks
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
A Critique of Adaptive Routing
A Critique of Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering
IBM Journal of Research and Development
The eDRAM based L3-Cache of the BlueGene/L Supercomputer Processor Node
SBAC-PAD '04 Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing
Architectures for ATM network survivability and their field deployment
IEEE Communications Magazine
Fast restoration of ATM networks
IEEE Journal on Selected Areas in Communications
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Virtual circuits (VCs) can reduce routing overheads with irregular topologies and provide support for a mix of quality of service (QoS) requirements. Information about network loads and traffic patterns may be used during circuit establishment to utilize network resources more efficiently than is practical with packet routing. Most VC schemes are static-each established VC remains unchanged until the connection is no longer needed. In contrast, we propose the dynamic virtual circuit (DVC) mechanism, which enables existing circuits to be quickly torn down in order to free up resources needed for other circuits or to re-establish circuits along routes that are better suited for current network conditions. We propose a deadlock avoidance technique, based on unconstrained routing of DVCs combined with a deadlock-free virtual network. We present a correctness proof for the scheme, describe key aspects of its implementation, and present performance evaluation results that explore its potential benefits.