On-chip versus off-chip test: an artificial dichotomy
ITC '98 Proceedings of the 1998 IEEE International Test Conference
How we test Siemens Embedded DRAM Cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Embedded DRAM built in self test and methodology for test insertion
Proceedings of the IEEE International Test Conference 2001
Issues and strategies for the physical design of system-on-a-chip ASICs
IBM Journal of Research and Development
Deadlock-free connection-based adaptive routing with dynamic virtual circuits
Journal of Parallel and Distributed Computing
Fault models for embedded-DRAM macros
Proceedings of the 46th Annual Design Automation Conference
Blue Gene/L compute chip: memory and Ethernet subsystem
IBM Journal of Research and Development
Blue Gene/L compute chip: synthesis, timing, and physical design
IBM Journal of Research and Development
Testing methodology of embedded DRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an overview of the macro design, architecture, and built-in self-test (BIST) implementation as part of the IBM third-generation embedded dynamic random-access memory (DRAM) for the IBM Blue Logic脗® 0.11-脗µm application-specific integrated circuit (ASIC) design system (CU-11). Issues associated with embedding DRAM in an ASIC design are identified and addressed, including fundamental DRAM core function, user interface, test, and diagnosis. Macro operation and organization are detailed and contrasted with traditional DRAM designs. The use of BIST, a key enabler for embedded DRAM, is discussed while highlighting innovations required by the embedded DRAM.