Blue Gene/L compute chip: synthesis, timing, and physical design

  • Authors:

  • A. A. Bright;R. A. Haring;M. B. Dombrowa;M. Ohmacht;D. Hoenicke;S. Singh;J. A. Marcella;R. F. Lembach;S. M. Douskey;M. R. Ellavsky;C. G. Zoellin;A. Gara

  • Affiliations:

  • IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Engineering and Technology Services, Rochester, Minnesota;IBM Engineering and Technology Services, Rochester, Minnesota;IBM Engineering and Technology Services, Rochester, Minnesota;IBM Engineering and Technology Services, Rochester, Minnesota;IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Boeblingen, Germany;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 2005

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Abstract

As one of the most highly integrated system-on-a-chip application-specific integrated circuits (ASICs) to date, the Blue Gene®/L compute chip presented unique challenges that required extensions of the standard ASIC synthesis, timing, and physical design methodologies. We describe the design flow from floorplanning through synthesis and timing closure to physical design, with emphasis on the novel features of this ASIC. Among these are a process to easily inject datapath placements for speed-critical circuits or to relieve wire congestion, and a timing closure methodology that resulted in timing closure for both nominal and worst-case timing specifications. The physical design methodology featured removal of the pre-physical-design buffering to improve routability and visualization of buses, and it featured strategic seeding of buffers to close wiring and timing and end up at 90% utilization of total chip area. Robustness was enhanced by using additional input/output (I/O) and internal decoupling capacitors and by increasing I/O-to-C4 wire widths.