A set of level 3 basic linear algebra subprograms
ACM Transactions on Mathematical Software (TOMS)
Built-in self-test support in the IBM engineering design system
IBM Journal of Research and Development
Test methodologies and design automation for IBM ASICs
IBM Journal of Research and Development
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
99% AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor
Proceedings of the IEEE International Test Conference 2001
Embedded DRAM built in self test and methodology for test insertion
Proceedings of the IEEE International Test Conference 2001
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Packaging the Blue Gene/L supercomputer
IBM Journal of Research and Development
Blue Gene/L torus interconnection network
IBM Journal of Research and Development
Accelerating time to market by reducing system test time
SE'07 Proceedings of the 25th conference on IASTED International Multi-Conference: Software Engineering
Overview of the Blue Gene/L system architecture
IBM Journal of Research and Development
Blue Gene/L compute chip: synthesis, timing, and physical design
IBM Journal of Research and Development
Blue Gene/L advanced diagnostics environment
IBM Journal of Research and Development
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The Blue Gene®/L compute (BLC) and Blue Gene/L link (BLL) chips have extensive facilities for control, bring-up, self-test, debug, and nonintrusive performance monitoring built on a serial interface compliant with IEEE Standard 1149.1. Both the BLL and the BLC chips contain a standard eServer™ chip JTAG controller called the access macro. For BLC, the capabilities of the access macro were extended 1) to accommodate the secondary JTAG controllers built into embedded PowerPC® cores; 2) to provide direct access to memory for initial boot code load and for messaging between the service node and the BLC chip; 3) to provide nonintrusive access to device control registers; and 4) to provide a suite of chip configuration and control registers. The BLC clock tree structure is described. It accommodates both functional requirements and requirements for enabling multiple built-in self-test domains, differentiated both by frequency and functionality. The chip features a debug port that allows observation of critical chip signals at full speed.