Methods in neuronal modeling: From synapses to networks
Methods in neuronal modeling: From synapses to networks
Wiring considerations in analog VLSI systems, with application to field-programmable networks
Wiring considerations in analog VLSI systems, with application to field-programmable networks
VLSI analogs of neuronal visual processing: a synthesis of form and function
VLSI analogs of neuronal visual processing: a synthesis of form and function
Fault-Containment in Cache Memories for TMR Redundant Processor Systems
IEEE Transactions on Computers
Pulsed Neural Networks
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
A Routing Methodology for Achieving Fault Tolerance in Direct Networks
IEEE Transactions on Computers
Theoretical Neuroscience: Computational and Mathematical Modeling of Neural Systems
Theoretical Neuroscience: Computational and Mathematical Modeling of Neural Systems
Immucube: Scalable Fault-Tolerant Routing for k-ary n-cube Networks
IEEE Transactions on Parallel and Distributed Systems
Heterogeneous Functional Units for High Speed Fault-Tolerant Execution Stage
PRDC '07 Proceedings of the 13th Pacific Rim International Symposium on Dependable Computing
A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR
EDCC-7 '08 Proceedings of the 2008 Seventh European Dependable Computing Conference
Understanding the interconnection network of SpiNNaker
Proceedings of the 23rd international conference on Supercomputing
Fault Tolerant Delay Insensitive Inter-chip Communication
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
The cat is out of the bag: cortical simulations with 109 neurons, 1013 synapses
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Overview of the Blue Gene/L system architecture
IBM Journal of Research and Development
Blue Gene/L compute chip: control, test, and bring-up infrastructure
IBM Journal of Research and Development
Soft Errors in Modern Electronic Systems
Soft Errors in Modern Electronic Systems
A real-time, FPGA based, biologically plausible neural network processor
ICANN'05 Proceedings of the 15th international conference on Artificial neural networks: formal models and their applications - Volume Part II
Simple model of spiking neurons
IEEE Transactions on Neural Networks
Hi-index | 0.00 |
SpiNNaker is a biologically-inspired massively-parallel computer designed to model up to a billion spiking neurons in real-time. A full-fledged implementation of a SpiNNaker system will comprise more than 10^5 integrated circuits (half of which are SDRAMs and half multi-core systems-on-chip). Given this scale, it is unavoidable that some components fail and, in consequence, fault-tolerance is a foundation of the system design. Although the target application can tolerate a certain, low level of failures, important efforts have been devoted to incorporate different techniques for fault tolerance. This paper is devoted to discussing how hardware and software mechanisms collaborate to make SpiNNaker operate properly even in the very likely scenario of component failures and how it can tolerate system-degradation levels well above those expected.