Fault Tolerant Delay Insensitive Inter-chip Communication

• Authors: Yebin Shi;Steve B. Furber;Jim Garside;Luis A. Plana
• Venue: ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
• Year: 2009

To the casual observer, glitches occurring in quasi delay-insensitive logic would appear to cause incorrect operation and render the circuits unusable. This paper presents an informal analysis of the effects of glitches occurring on the long interconnect ...