Proceedings of the 39th annual Design Automation Conference
Extending OPMISR beyond 10x Scan Test Efficiency
IEEE Design & Test
Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits
Journal of Electronic Testing: Theory and Applications
On test data compression and n-detection test sets
Proceedings of the 40th annual Design Automation Conference
Embedded Deterministic Test for Low-Cost Manufacturing
IEEE Design & Test
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units
IEEE Transactions on Computers
IEEE Transactions on Computers
An Arithmetic Structure for Test Data Horizontal Compression
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes
Journal of Electronic Testing: Theory and Applications
Compact Dictionaries for Fault Diagnosis in Scan-BIST
IEEE Transactions on Computers
Changing the Scan Enable during Shift
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
ELF-Murphy Data on Defects and Test Sets
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Scalable selector architecture for x-tolerant deterministic BIST
Proceedings of the 41st annual Design Automation Conference
On Compacting Test Response Data Containing Unknown Values
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Technique for High Ratio LZW Compression
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Achieving high encoding efficiency with partial dynamic LFSR reseeding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Journal of Electronic Testing: Theory and Applications
Response compaction with any number of unknowns using a new LFSR architecture
Proceedings of the 42nd annual Design Automation Conference
Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
Response shaper: a novel technique to enhance unknown tolerance for output response compaction
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Concurrent core test for SOC using shared test set and scan chain disable
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A flexible and scalable methodology for GHz-speed structural test
Proceedings of the 43rd annual Design Automation Conference
Using reiterative LFSR based X-masking to increase output compression in presence of unknowns
Proceedings of the 18th ACM Great Lakes symposium on VLSI
On reliable modular testing with vulnerable test access mechanisms
Proceedings of the 45th annual Design Automation Conference
State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores
Proceedings of the conference on Design, automation and test in Europe
DX-compactor: distributed X-compaction for SoCs
Proceedings of the 19th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
X-tolerant Test Data Compaction with Accelerated Shift Registers
Journal of Electronic Testing: Theory and Applications
Blue Gene/L compute chip: control, test, and bring-up infrastructure
IBM Journal of Research and Development
X-align: improving the scan cell observability of response compactors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On compaction utilizing inter and intra-correlation of unknown states
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On test generation with test vector improvement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fully X-tolerant, very high scan compression
Proceedings of the 47th Design Automation Conference
A combinatorial approach to X-tolerant compaction circuits
IEEE Transactions on Information Theory
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Autoscan: a scan design without external scan inputs or outputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Generation of mixed test sets for transition faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computing two-pattern test cubes for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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