Using a single input to support multiple scan chains
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Very Low Cost Testers: Opportunities and Challenges
IEEE Design & Test
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Adapting an SoC to ATE Concurrent Test Capabilities
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Reducing Power Dissipation during Test Using Scan Chain Disable
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Test Economics for Multi-site Test with Modern Cost Reduction Techniques
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
IEEE Transactions on Computers
Application of Arithmetic Coding to Compression of VLSI Test Data
IEEE Transactions on Computers
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
ITC '04 Proceedings of the International Test Conference on International Test Conference
DATA COMPRESSION FOR MULTIPLE SCAN CHAINS USING DICTIONARIES WITH CORRECTIONS
ITC '04 Proceedings of the International Test Conference on International Test Conference
Test pattern generation and clock disabling for simultaneous test time and power reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test cost reduction for SoC using a combined approach to test data compression and test scheduling
Proceedings of the conference on Design, automation and test in Europe
Optimized integration of test compression and sharing for SOC testing
Proceedings of the conference on Design, automation and test in Europe
| Hi-index | 0.00 |
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. Prior to test, the test sets corresponding to cores under test (CUT) are merged by using the proposed merging algorithm to obtain a shared test set with minimum size. During test, the on-chip scan chain disable signal (SCDS) generator is employed to retrieve the original test vectors from the shared test set. The approach is non-intrusive and automatic test pattern generator (ATPG) independent. Moreover, the approach can reduce test cost further by combining with general test compression/decompression technique. Experimental results for ISCAS 89 benchmark circuits have proven the efficiency of the proposed approach.