Hybrid BIST Based on Repeating Sequences and Cluster Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Concurrent core test for SOC using shared test set and scan chain disable
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Survey of Test Vector Compression Techniques
IEEE Design & Test
Scan-BIST based on cluster analysis and the encoding of repeating sequences
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CacheCompress: a novel approach for test data compression with cache for IP embedded cores
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A selective pattern-compression scheme for power and test-data reduction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
GECOM: test data compression combined with all unknown response masking
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
On Detection of Bridge Defects with Stuck-at Tests
IEICE - Transactions on Information and Systems
Reducing the storage requirements of a test sequence by using a background vector
Proceedings of the Conference on Design, Automation and Test in Europe
On reducing test power and test volume by selective pattern compression schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression using efficient bitmask and dictionary selection methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compression-aware capture power reduction for at-speed testing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
Test data compression using selective encoding of scan slices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test Data Compression Using Selective Sparse Storage
Journal of Electronic Testing: Theory and Applications
Test data compression using interval broadcast scan for embedded cores
Microelectronics Journal
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Reducing test application time and test data volume are major challenges in SoC design. In the case of IP cores, where no structural information is available, a common strategy is to compress the test data TD provided by the core vendor into an encoded format TE. Only the smaller set TE is stored on the ATE, and during test the original test data TD are regenerated by an on-chip decompressor. However, most of the encoding schemes suffer from two major drawbacks: Firstly, the irregularity of the encoded test data requires a complex test control including a handshake between the ATE and the system under test. Secondly, compression and decompression is very efficient for circuits with a single scan chain, however the extension to multiple scan chains requires either a separate decompressor for each chain or a serialization of the test data. So far, only a few approaches have been proposed trying to overcome these problems. Instead of dealing with the test vectors these approaches work with the slices to be fed into the scan chains, but they still allow a considerable degree of irregularity in the test application process. In this paper we propose a new dictionary based compression scheme which allows a fully regular test application while keeping the storage requirements low. Due to the regularity of the scheme the advantages of a multiple-scan architecture are preserved, and very low test times can be achieved.