IEEE Transactions on Computers - Special issue on fault-tolerant computing
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Analysis and Design of Optimal Combinational Compactors
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
CircularScan: A Scan Architecture for Test Cost Reduction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
ITC '04 Proceedings of the International Test Conference on International Test Conference
Channel Masking Synthesis for Efficient On-Chip Test Compression
ITC '04 Proceedings of the International Test Conference on International Test Conference
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
ITC '04 Proceedings of the International Test Conference on International Test Conference
DATA COMPRESSION FOR MULTIPLE SCAN CHAINS USING DICTIONARIES WITH CORRECTIONS
ITC '04 Proceedings of the International Test Conference on International Test Conference
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Survey of Test Vector Compression Techniques
IEEE Design & Test
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
This paper introduces GECOM technology, a novel test compression method with seamless integration of test GEneration, test COmpression (i.e. integrated compression on scan stimulus and masking bits) and all unknown scan responses Masking for manufacturing test cost reduction. Unlike most of prior methods, the proposed method considers the unknown responses during ATPG procedure and selectively encodes the specified 1 or 0 bits (either 1s or 0s) in scan slices for compression while at the same time masks the unknown responses before sending them to the response compactor. The proposed GECOM technology consists of GECOM architecture and GECOM ATPG technique. In the GECOM architecture, for a circuit with N internal scan chains, only c tester channels, where c = [log2 N] +2, are required. GECOM ATPG generates test patterns for the GECOM architecture thus not only the scan inputs could be efficiently compressed but also all the unknown responses would be masked. Experimental results on both benchmark circuits and real industrial designs indicated the effectiveness of the proposed GECOM technique.