Proceedings of the 1st conference on Computing frontiers
Response compaction with any number of unknowns using a new LFSR architecture
Proceedings of the 42nd annual Design Automation Conference
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Coverage loss by using space compactors in presence of unknown values
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 43rd annual Design Automation Conference
A hybrid scheme for compacting test responses with unknown values
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
GECOM: test data compression combined with all unknown response masking
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A combinatorial approach to X-tolerant compaction circuits
IEEE Transactions on Information Theory
Improving compressed test pattern generation for multiple scan chain failure diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
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Scan and logic built-in self-test (BIST) are increasinglyused to reduce test cost. In these test architectures, manyinternal signals are observed through a small number ofoutput pins or into a small signature analyzer, requiring acombinational space compactor. This paper analyzes thebasic requirements of compactors to support efficient testand diagnosis, focusing on practical compactors where allinputs have fanout two. We show how graph theory can beused to model compactors and design compactors withrobust non-aliasing properties that have minimal area anddelay overhead and are independent of the test set, the faultmodel and the circuit tested.