A Totally Self-Checking Error Indicator
IEEE Transactions on Computers
Parallel Testing of Multi-port Static Random Access Memories for BIST
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
On-Line Testing Scheme for Clock's Faults
Proceedings of the IEEE International Test Conference
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Two-dimensional test data compression for scan-based deterministic BIST
Proceedings of the IEEE International Test Conference 2001
Debug methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
Test methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
Proceedings of the IEEE International Test Conference 2001
Compact and Highly Testable Error Indicator for Self-Checking Circuits
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
An asynchronous totally self-checking two-rail code error indicator
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Analysis and Design of Optimal Combinational Compactors
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Test and On-line Debug Capabilities of IEEE Std 1149.1 in UltraSPARC"-III Microprocessor
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Support for Debugging in the Alpha 21364 Microprocessor
ITC '02 Proceedings of the 2002 IEEE International Test Conference
ITC '02 Proceedings of the 2002 IEEE International Test Conference
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Clock Faults' Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
IEEE Transactions on Computers
High Speed and Highly Testable Parallel Two-Rail Code Checker
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Low Cost and High Speed Embedded Two-Rail Code Checker
IEEE Transactions on Computers
Elimination of Traditional Functional Testing of Interface Timings at Intel
ITC '04 Proceedings of the International Test Conference on International Test Conference
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We analyze the risks associated with faults affecting some Design For Testability (DFT) features employed within todays' high performance microprocessors. We will show that, because of the occurrence of internal faults, some of these structures may become useless, with consequent dramatic impact on test effectiveness and product quality. We borrow the Fault Secure property, that is well known for Self-Checking Circuits, for DFT structures. We will show that it guarantees that no escapes or false acceptance of faulty products may occur because of faults affecting the employed DFT structures. We will discuss the Fault Secureness of the considered DFT structures. We will provide some examples of how the non Fault Secure ones can be modified to meet the Fault Secure goal, thus avoiding their prospected detrimental effect on next generation high performance microprocessors test effectiveness and quality.