Test and On-line Debug Capabilities of IEEE Std 1149.1 in UltraSPARC"-III Microprocessor

Authors:
Farideh Golshan
Affiliations:
-
Venue:
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Year:
2000

Citing 2
Cited 5

The SPARC architecture manual (version 9)

The SPARC architecture manual (version 9)
Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor

Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test

Fault secureness need for next generation high performance microprocessor design for testability structures

Proceedings of the 1st conference on Computing frontiers
Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores

IEEE Transactions on Computers
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?

IEEE Transactions on Computers
A scan cell design for scan-based debugging of an SoC with multiple clock domains

IEEE Transactions on Circuits and Systems II: Express Briefs
Clock Faults Induced Min and Max Delay Violations

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.01

Visualization

Abstract

The IEEE Std 1149.1[1] features have been essential in systemand chip debug, test and manufacturing of Ultra-SPARC-III product. Several key testability features wereachieved by adding a suite of customized instructions andlogic to the chip core and I/Os to allow test and debug whenin test mode or debug during normal operations. In addition,due to the design of high speed I/Os, extra logic wasadded to Boundary-Scan to maintain compliancy and providesupport for all test and debug features. This paper discussesthe above features and their logic implementations.