Clock Faults Induced Min and Max Delay Violations

Authors:
D. Rossi;M. Omaña;J. M. Cazeaux;C. Metra;T. M. Mak
Affiliations:
DEI --- ARCES, University of Bologna, Bologna, Italy;DEI --- ARCES, University of Bologna, Bologna, Italy;DEI --- ARCES, University of Bologna, Bologna, Italy;DEI --- ARCES, University of Bologna, Bologna, Italy;GlobalFoundries, Sunnyvale, USA
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2014

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Abstract

In this paper, we show that clock faults producing duty-cycle variations, which have been proven very likely, can give rise to min or max delay violations. This mandates new, specific testing approaches for clock faults, to avoid them to compromise the system correct operation in the field, with dramatic effects on product quality and defect level. We then introduce a new scheme that can be employed to detect the clock faults causing duty-cycle variations.