Circuit Design Techniques for a Gigahertz Integer Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A Coarse-Grain Phased Logic CPU
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Correction to "Statistical clock skew modeling with data delay variations"
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of blocking dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical Clock Skew Analysis Considering Intra-Die Process Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A multiple level network approach for clock skew minimization with process variations
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A low-power reduced swing global clocking methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical Analysis of Clock Skew Variation in H-Tree Structure
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Clock trees: differential or single ended?
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A Coarse-Grain Phased Logic CPU
IEEE Transactions on Computers
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Hold time validation on silicon and the relevance of hazards in timing analysis
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 2006 international symposium on Low power electronics and design
Improvement of power distribution network using correlation-based regression analysis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast and power-area-efficient accumulator for flying-adder frequency synthesizer
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Impact of device variability in the communication structures for future synchronous SoC designs
SOC'09 Proceedings of the 11th international conference on System-on-chip
Flip-flop energy/performance versus clock slope and impact on the clock network design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Comparison of high-performance VLSI adders in the energy-delay space
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effect of process variations in 3D global clock distribution networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
On-chip ring network designs for hard-real time systems
Proceedings of the 21st International conference on Real-Time Networks and Systems
Clock Faults Induced Min and Max Delay Violations
Journal of Electronic Testing: Theory and Applications
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Accurate clock skew budgets are important for microprocessor designers to avoid hold-time failures and to properly allocate resources when optimizing global and local paths. Many published clock skew budgets neglect voltage jitter and process variation, which are becoming dominant factors in otherwise balanced H-trees. However, worst-case process variation assumptions are severely pessimistic. This paper describes the major sources of clock skew in a microprocessor using a modified H-tree and applies the model to a second-generation Itanium-M processor family microprocessor currently under design. Monte Carlo simulation is used to develop statistical clock skew budgets for setup and hold time constraints in a four-level skew hierarchy. Voltage jitter through the phase locked loop (PLL) and clock buffers accounts for the majority of skew budgets. We show that taking into account the number of nearly critical paths between clocked elements at each level of the skew hierarchy and variations in the data delays of these paths reduces the difference between global and local skew budgets by more than a factor of two. Another insight is that data path delay variability limits the potential cycle-time benefits of active deskew circuits because the paths with the worst skew are unlikely to also be the paths with the longest data delays.