High-speed digital design: a handbook of black magic
High-speed digital design: a handbook of black magic
Stari: a technique for high-bandwidth communication
Stari: a technique for high-bandwidth communication
The case for a single-chip multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
High speed CMOS design styles
Interfacing synchronous and asynchronous modules within a high-speed pipeline
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Statistical clock skew modeling with data delay variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Power and performance evaluation of globally asynchronous locally synchronous processors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Pausible Clocking: A First Step Toward Heterogeneous Systems
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Low-Power Self-Timed Viterbi Decoder
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Low-latency plesiochronous data retiming
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
AMULET3: A 100 MIPS Asynchronous Embedded Processor
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Anomalous Behavior of Synchronizer and Arbiter Circuits
IEEE Transactions on Computers
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test
IEEE Transactions on Computers
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Reasoning about synchronization in GALS systems
Formal Methods in System Design
A predictive synchronizer for periodic clock domains
Formal Methods in System Design
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Proceedings of the 44th annual Design Automation Conference
Integration, the VLSI Journal
A Highly Scalable GALS Crossbar Using Token Ring Arbitration
IEEE Design & Test
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis
Electronic Notes in Theoretical Computer Science (ENTCS)
Proceedings of the 7th ACM international conference on Computing frontiers
A flexible communication scheme for rationally-related clock frequencies
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DVB-DSNG modem high level synthesis in an optimized latency insensitive system context
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
StarSync: An extendable standard-cell mesochronous synchronizer
Integration, the VLSI Journal
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With increasing integration densities, large chip designs are commonly partitioned into multiple clock domains. Ehile the computation within each individual domain may be synchronous, the interfaces between these domains often use asynchronous methods. One such approach is the STARI technique [12, 13] where a self-timed FIFO compensates for clock-skew between the sender and receiver. We present implementations of STARI where the FIFO consists of a single, handshaking stage. We start with the simplest case where the sender and receiver operate at exactly the same frequency with an unknown skew. We then generalize this design for links with clocks whose frequencies are rational multiples of each other; clocks whose frequencies are closely matched, and arbitrary clocks. We show that in each of these cases, the STARI interface can exploit the stability of typical clocks to achieve low latencies and negligible probabilities of synchronization failure using very simple hardware.