Two efficient synchronous ↔ asynchronous converters well-suited for network on chip in GALS architectures

Authors:
A. Sheibanyrad;A. Greiner
Affiliations:
The University of Pierre and Marie Curie, Paris, France;The University of Pierre and Marie Curie, Paris, France
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

This paper presents two high-throughput, low-latency converters that can be used to convert synchronous communication protocol to asynchronous one and vice versa. These two hardware components have been designed to be used in Multi-Processor System on Chip respecting the GALS (Globally Asynchronous Locally Synchronous) paradigm and communicating by a fully asynchronous Network on Chip (NoC). The proposed architecture is rather generic, and allows the system designer to make various trade-off between latency and robustness, depending on the selected synchronizer. These converters have been physically implemented with the portable ALLIANCE CMOS standard cell library and the architecture has been evaluated by SPICE simulation for a 90nm CMOS fabrication process.